Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 554 of 994
REJ09B0452-0100
Bit Bit
Name
Initial
Value R/W Description
0 ACKB 0
R/W
Acknowledge Bit
Stores acknowledge data.
The bit function varies depending on transmit mode
and receive mode.
Transmit mode:
Holds the acknowledge data returned by the receiving
device.
[Setting condition]
When 1 is received as the acknowledge bit when
ACKE = 1 in transmit mode
[Clearing conditions]
•
When 0 is received as the acknowledge bit when
ACKE = 1 in transmit mode
•
When 0 is written to the ACKE bit
Receive mode:
Sets the acknowledge data to be returned to the
transmitting device.
0: Returns 0 as acknowledge data after data reception
1: Returns 1 as acknowledge data after data reception
When this bit is read, the value loaded from the bus
line (returned by the receiving device) is read in
transmission (when TRS = 1). In reception (when TRS
= 0), the value set by internal software is read.
When this bit is written, acknowledge data that is
returned after receiving is rewritten regardless of the
TRS value.
Note: When, in transmit mode, this bit has been
overwritten by a bit manipulation instruction with a
value other than that of the ACKB flag in ICSR, the
value of the ACKB bit as the acknowledge data setting
for receive mode is overwritten by this value. Thus,
always reset the acknowledge data when switching to
receive mode.
Write 0 to the ACKE bit to clear the ACKB flag to 0 in
the following cases:
in master mode—before transmission is ended and a
stop condition is generated; and
in slave mode—before transmission is ended and SDA
is released to allow a master device to issue a stop
condition.
Note:
*
Only 0 can be written to clear the flag.
Summary of Contents for H8S/2100 Series
Page 2: ...Rev 1 00 Apr 28 2008 Page ii of xxvi...
Page 54: ...Section 1 Overview Rev 1 00 Apr 28 2008 Page 28 of 994 REJ09B0452 0100...
Page 92: ...Section 2 CPU Rev 1 00 Apr 28 2008 Page 66 of 994 REJ09B0452 0100...
Page 158: ...Section 5 Interrupt Controller Rev 1 00 Apr 28 2008 Page 132 of 994 REJ09B0452 0100...
Page 244: ...Section 8 8 Bit PWM Timer PWMU Rev 1 00 Apr 28 2008 Page 218 of 994 REJ09B0452 0100...
Page 330: ...Section 10 16 Bit Timer Pulse Unit TPU Rev 1 00 Apr 28 2008 Page 304 of 994 REJ09B0452 0100...
Page 416: ...Section 13 8 Bit Timer TMR Rev 1 00 Apr 28 2008 Page 390 of 994 REJ09B0452 0100...
Page 612: ...Section 18 I 2 C Bus Interface IIC Rev 1 00 Apr 28 2008 Page 586 of 994 REJ09B0452 0100...
Page 706: ...Section 20 LPC Interface LPC Rev 1 00 Apr 28 2008 Page 680 of 994 REJ09B0452 0100...
Page 752: ...Section 21 FSI Interface Rev 1 00 Apr 28 2008 Page 726 of 994 REJ09B0452 0100...
Page 774: ...Section 23 RAM Rev 1 00 Apr 28 2008 Page 748 of 994 REJ09B0452 0100...
Page 1008: ...Section 28 Electrical Characteristics Rev 1 00 Apr 28 2008 Page 982 of 994 REJ09B0452 0100...
Page 1020: ...Rev 1 00 Apr 28 2008 Page 994 of 994 REJ09B0452 0100...
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Page 1024: ...H8S 2117R Group Hardware Manual...