Renesas H8S/2100 Series, Hardware Manual

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Section 8 8-Bit PWM Timer (PWMU)
Rev. 1.00 Apr. 28, 2008 Page 209 of 994
REJ09B0452-0100
8.3.6 PWM Duty Setting Registers 0 to 5 (PWMREG0 to PWMREG5)
PWMREG0 to PWMREG5 are 8-bit readable/writable registers used to set the high period (duty)
of the PWM output pulse. The initial value is H'00.
(1) 8-Bit Single Pulse Mode
Directly set the high period of the pulse for PWM output. With PWMREG registers, the duty
cycle of the PWM output pulse is specified as a value from 0/255 to 255/255 with a resolution of
1/255.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
Output pulse high period = (PWM cycle
×
m) / 255 (0
≤
m
≤
255)
(2) 16-Bit Single Pulse Mode
Directly set the high period of the pulse for PWM output. With cascade-connected PWMREG
registers, the duty cycle of the PWM output pulse is specified as a value from 0/65535 to
65535/65535.
When the PWMREG value is m, the high period of the output pulse is calculated as follows:
Output pulse high period = (PWM cycle
×
m) / 65535 (0
≤
m
≤
65535)
Set the respective high-level pulse periods by using the following register combinations (cascaded
connection): PWMREG1 (higher order) and PWMREG0 (lower order), PWMREG3 (higher order)
and PWMREG2 (lower order), and PWMREG5 (higher order) and PWMREG4 (lower order).
(3) 8-Bit Pulse Division Mode
Specify the basic pulse duty cycle and the number of additional pulses for PWM output. The
higher-order four bits of the PWMREG setting specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16, and the lower-order four bits specify the number of pulses to be
added within the conversion period comprising the basic pulses.