Renesas H8S/2100 Series, Hardware Manual

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Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 1.00 Apr. 28, 2008 Page 261 of 994
REJ09B0452-0100
Bit Bit Name
Initial
value R/W
Description
3 TGFD 0 R/(W) * Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channel 0.
In channels 1 and 2, bit 3 is reserved. It is always read
as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRD while TGRD is functioning as
output compare register
•
When TCNT value is transferred to TGRD by input
capture signal while TGRD is functioning as input
capture register
[Clearing condition]
When 0 is written to TGFD after reading TGFD = 1
2 TGFC 0 R/(W)
*
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channel 0.
In channels 1 and 2, bit 2 is reserved. It is always read
as 0 and cannot be modified.
[Setting conditions]
•
When the TCNT = TGRC while TGRC is functioning
as output compare register
•
When TCNT value is transferred to TGRC by input
capture signal while TGRC is functioning as input
capture register
[Clearing condition]
When 0 is written to TGFC after reading TGFC = 1