Renesas H8S/2100 Series, Hardware Manual

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Section 18 I
2
C Bus Interface (IIC)
Rev. 1.00 Apr. 28, 2008 Page 573 of 994
REJ09B0452-0100
SDA
(master output)
SDA
(slave output)
2 1 2 1 4 3 6 5 8 7 9
Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRF
IRIC
ICDRS
ICDRR
SCL
(master output)
SCL
(slave output)
R/
W
R/
W
Undefined value
[8] IRIC clear [10] ICDR read (dummy read)
User processing
2 1 2 1 4 3 6 5 8 7 9
SCL
(Pin waveform)
Start condition generation
Slave address Data 1
[6]
A
R/
W
[7] SCL is fixed low until ICDR is read
[2] ICDR read
Interrupt
request
occurrence
Figure 18.14 Example of Slave Receive Mode Operation Timing (1) (MLS = 0)
SDA
(master output)
SDA
(slave output)
2 1 4 3 6 5 8 7 9 8 9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
SCL
(slave output)
[8] IRIC clear
[12] IRIC clear
[9] Set ACKB=1
[5] ICDR read (Data (n-1))
[10] ICDR read
(Data (n))
User processing
Data (n)
Data (n-1)
Data (n-2)
[6] [6]
[11]
A A
Stop condition
generation
[7] SCL is fixed low until ICDR is read
[7] SCL is fixed low until ICDR is read
Data (n-1)
Data (n)
Data (n)
[8] IRIC clear
Data (n-1)
Figure 18.15 Example of Slave Receive Mode Operation Timing (2) (MLS = 0)