Renesas H8S/2100 Series, Hardware Manual

Page: 150 / 1024

Section 5 Interrupt Controller
Rev. 1.00 Apr. 28, 2008 Page 124 of 994
REJ09B0452-0100
5.6.3 Interrupt Exception Handling Sequence
Figure 5.10 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
(14)
(12)
(10)
(6)
(4)
(2)
(1)
(5)
(7)
(9)
(11)
(13)
Prefetch of instruction in interrupt handling routine
Vector fetch
Stack access
Instruction prefetch
Internal processing
Internal processing
Interrupt is accepted
Interrupt level determination and wait for end of instruction
Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data bus
φ
(3)
(1) (2) (4) (3) (5) (7)
Instruction prefetch address (Not executed. Address is saved as PC contents, becoming return address.) Instruction code (Not executed.) Instruction prefetch address (Not executed.) SP – 2 SP – 4
Saved PC and CCR Vector address Start address of interrupt handling routine (contents of vector address) Start address of interrupt handling routine ((13) = (10) (12)) First instruction in interrupt handling routine
(6) (8) (9) (11) (10) (12) (13) (14)
(8)
Figure 5.10 Interrupt Exception Handling