Renesas H8S/2100 Series, Hardware Manual

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Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 1.00 Apr. 28, 2008 Page 321 of 994
REJ09B0452-0100
When the CMMS bit in TCMIER is set to 1, cycle measurement is performed only while the
TCMMCI signal is high (MCICTL in TCMCSR is 0). Figure 11.9 shows an example of timing in
cycle measurement when the CMMS bit is set to 1.
φ
TCMCYI
TCMMCI
TCMCNT
H'0006 M 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 A B 0 1 2 3 4
M H'0007
H'000B
L
5
TCMICR
Figure 11.9 Example of Timing in Cycle Measurement when the CMMS Bit is Set to 1
(3) Determination of External Event (TCMCYI) Stoppage
The timer overflow flag can be used to determine the external event (TCMCYI) stopped state.
Either of two sets of conditions represents the external event stopped state.
The external event can be considered to have stopped when a timer overflow is generated within
the period from the start of cycle measurement mode to detection of the first edge (rising or falling
as selected with the IEDG bit in TCMCR).
Figure 11.10 shows an example of the timing of the external event stopped state (1).
φ
TCMCYI
Start of measurement
TCMMDS
MAXOVF/
MINUDF
TCMCNT
H'0000 H'FFFF H'0000 N H'0000 H'0001 H'0002
OVF
Determined as external event stopped state
Figure 11.10 Example of Timing in External Event Stopped State (1)