Renesas H8S/2100 Series, Hardware Manual

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Section 26 Power-Down Modes
Rev. 1.00 Apr. 28, 2008 Page 841 of 994
REJ09B0452-0100
Section 26 Power-Down Modes
For operating modes after the reset state is cancelled, this LSI has four power-down operating
modes in which power consumption is significantly reduced. In addition, there is also module stop
mode in which reduced power consumption can be achieved by individually stopping on-chip
peripheral modules.
•
Medium-speed mode
System clock frequency for the CPU operation can be selected as
φ
/2,
φ
/4,
φ
/8,
φ
/16 or
φ
/32.
•
Sleep mode
The CPU stops but on-chip peripheral modules continue operating.
•
Watch mode
The CPU stops, but on-chip peripheral module WDT_1 and CIR continue operating.
•
Software standby mode
The clock pulse generator stops, and the CPU and on-chip peripheral modules stop operating.
•
Module stop mode
Independently of above operating modes, on-chip peripheral modules that are not used can be
stopped individually.
26.1 Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR)
must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register
(STCR). For details on the PSS bit in TSCR_1 (WDT_1), see TCSR_1 in section 13.3.5, Timer
Control/Status Register (TCSR).
Table 26.1 Register Configuration
Register Name Abbreviation R/W Initial Value Address
Data Bus
Width
Standby control register SBYCR R/W H'00 H'FF84 8
Low power control register LPWRCR R/W H'00 H'FF85 8
Module stop control register H MSTPCRH R/W H'3F H'FF86 8
Module stop control register L MSTPCRL R/W H'FF H'FF87 8
Module stop control register A MSTPCRA R/W H'FC H'FE7E 8
Module stop control register B MSTPCRB R/W H'FF H'FE7F 8