Renesas H8S/2100 Series, Hardware Manual

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Section 11 16-Bit Cycle Measurement Timer (TCM)
Rev. 1.00 Apr. 28, 2008 Page 311 of 994
REJ09B0452-0100
11.3.6 TCM Status Register (TCMCSR)
TCMCSR is an 8-bit readable/writable register that controls operation of the interrupt sources.
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W) * Timer Overflow
This flag indicates that the TCMCNT has overflowed.
[Setting condition]
Overflow of TCMCNT (change in value from H'FFFF to
H'0000)
[Clearing condition]
Reading OVF when OVF = 1 and then writing 0 to OVF.
6 MAXOVF 0 R/(W) * Measurement Period Upper Limit Overflow
This flag indicates that the measured number of cycles of
the waveform for measurement in cycle measurement mode
has reached the upper limit set in TCMMLCM, causing an
overflow.
[Setting condition]
A greater value for TCMICR than TCMMLCM
[Clearing condition]
Reading MAXOVF when MAXOVF = 1 and then writing 0 to
MAXOVF
5 CMF 0 R/(W) * Compare Match Flag (only valid in timer mode)
[Setting condition]
When the values in TCMCNT and TCMMLCM match.
[Clearing condition]
Reading CMF when CMF = 1 and then writing 0 to CMF
Note: CMF is not set in cycle measurement mode, even
when the values in TCMCNT and TCMMLCM match.
4 CKSEG 0 R/W External Clock Edge Select
When bits CKS2 to CKS0 in TCMCR are set to B'111, this
bit selects the edge for counting of external count clock
edge.
0: Count falling edges of the external clock.
1: Count rising edges of the external clock.