Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
18-26 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Arithmetic average (or mean) is calculated by summing the four byte oper-
ands, then shifting right two places to divide by four.
When the intermediate sum is not evenly divisible by 4, precision may be
lost.
The user has two options to bias the result–truncation or biased rounding.
See “Rounding and Truncating” on page 1-19 for a description of unbi-
ased rounding and truncating behavior.
The
RND_MOD
bit in the
ASTAT
register has no bearing on the rounding
behavior of this instruction.
The only valid input source register pairs are
R1:0
and
R3:2
.
The Quad 8-Bit Average – Half-Word instruction provides byte align-
ment directly in the source register pairs
src_reg_0
(typically
R1:0
) and
src_reg_1
(typically
R3:2
) based only on the
I0
register . The byte align-
ment in both source registers must be identical since only one register
specifies the byte alignment for them both.
The relationship between the I-register bits and the byte alignment is
illustrated in
Table 18-19 .
In the default source order case (for example, not the (R) syntax), assume a
source register pair contains the data shown in
Table 18-19 .
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
Table 18-18. And the versions that load the result into the higher byte –
RNDH and TH – produce:
31................24 23................16 15..................8 7....................0
dest_reg: avg(y3, y2, z3,
z2)
0 . . . . . . 0 avg(y1, y0, z1,
z0)
0 . . . . . . 0