Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
18-20 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Arithmetic average (or mean) is calculated by summing the two operands,
then shifting right one place to divide by two.
The user has two options to bias the result–truncation or rounding up. By
default, the architecture rounds up the mean when the sum is odd. How-
ever, the syntax supports optional truncation.
See “Rounding and Truncating” on page 1-19 for a description of biased
rounding and truncating behavior.
The
RND_MOD
bit in the
ASTAT
register has no bearing on the rounding
behavior of this instruction.
The only valid input source register pairs are
R1:0
and
R3:2
.
The Quad 8-Bit Average – Byte instruction provides byte alignment
directly in the source register pairs
src_reg_0
and
src_reg_1
based on
index registers
I0
and
I1
.
• The two LSBs of the
I0
register determine the byte alignment for
source register pair
src_reg_0
(typically
R1:0
).
• The two LSBs of the
I1
register determine the byte alignment for
source register pair
src_reg_1
(typically
R3:2
).
Table 18-11. Source Registers Contain
31................24 23................16 15..................8 7....................0
aligned_src_reg_0: y3 y2 y1 y0
aligned_src_reg_1: z3 z2 z1 z0
Table 18-12. Destination Registers Receive
31................24 23................16 15..................8 7....................0
dest_reg: avg(y3, z3) avg(y2, z2) avg(y1, z1) avg(y0, z0)