Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 1-21
Introduction
Automatic Circular Addressing
The Blackfin processor provides an optional circular (or “modulo”)
addressing feature that increments an Index Register (
Ireg
) through a pre-
defined address range, then automatically resets the
Ireg
to repeat that
range. This feature improves input/output loop performance by eliminat-
ing the need to manually reinitialize the address index pointer each time.
Circular addressing is useful, for instance, when repetitively loading or
storing a string of fixed-sized data blocks.
The circular buffer contents must meet the following conditions:
• The maximum length of a circular buffer (that is, the value held in
any L register) must be an unsigned number with magnitude less
than 2
31
.
• The magnitude of the modifier should be less than the length of
the circular buffer.
• The initial location of the pointer I should be within the circular
buffer defined by the base B and length L.
If any of these conditions is not satisfied, then processor behavior is not
specified.
There are two elements of automatic circular addressing:
• Indexed address instructions
• Four sets of circular addressing buffer registers composed of one
each
Ireg
,
Breg
, and
Lreg
(i.e.,
I0/B0/L0
,
I1/B1/L1
,
I2/B2/L2
, and
I3/B3/L3
)
To qualify for circular addressing, the indexed address instruction must
explicitly modify an Index Register. Some indexed address instructions use
a Modify Register (
Mreg
) to increment the
Ireg
value. In that case, any
Mreg
can be used to increment any
Ireg
. The
Ireg
used in the instruction
specifies which of the four circular buffer sets to use.