Analog Devices ADSP-BF53x Blackfin, Reference

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Event Handling
1-6 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
External Memory
External (off-chip) memory is accessed via the External Bus Interface Unit
(EBIU). This 16-bit interface provides a glueless connection to a bank of
synchronous DRAM (SDRAM) and as many as four banks of asynchro-
nous memory devices including flash memory, EPROM, ROM, SRAM,
and memory-mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed to inter-
face to up to 512M bytes of SDRAM (certain products have SDRAM up
to 128M bytes).
The asynchronous memory controller can be programmed to control up
to four banks of devices. Each bank occupies a 1M byte segment regardless
of the size of the devices used, so that these banks are only contiguous if
each is fully populated with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All resources are
mapped through the flat 32-bit address space. Control registers for
on-chip I/O devices are mapped into memory-mapped registers (MMRs)
at addresses near the top of the 4G byte address space. These are separated
into two smaller blocks: one contains the control MMRs for all core func-
tions and the other contains the registers needed for setup and control of
the on-chip peripherals outside of the core. The MMRs are accessible only
in Supervisor mode. They appear as reserved space to on-chip peripherals.
Event Handling
The event controller on the Blackfin processor handles all asynchronous
and synchronous events to the processor. The processor event handling
supports both nesting and prioritization. Nesting allows multiple event
service routines to be active simultaneously. Prioritization ensures that