Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 4-55
Program Sequencer
Logging of Nested Interrupt Requests
The System Interrupt Controller () detects level-sensitive interrupt
requests from the peripherals. The Core Event Controller (CEC) provides
edge-sensitive detection for its general-purpose interrupts (
IVG7-IVG15
).
Consequently, the SIC generates a synchronous interrupt pulse to the
CEC and then waits for interrupt acknowledgement from the CEC. When
the interrupt has been acknowledged by the core (via assertion of the
appropriate
IPEND
output), the SIC generates another synchronous inter-
rupt pulse to the CEC if the peripheral interrupt is still asserted. This way,
the system does not lose peripheral interrupt requests that occur during
servicing of another interrupt.
Multiple interrupt sources can map to a single core processor general-pur-
pose interrupt. Because of this, multiple pulse assertions from the SIC can
occur simultaneously, before, or during interrupt processing for an inter-
rupt event that is already detected on this interrupt input. For a shared
interrupt, the
IPEND
interrupt acknowledge mechanism described above
re-enables all shared interrupts. If any of the shared interrupt sources are
still asserted, at least one pulse is again generated by the SIC. The Inter-
rupt Status registers indicate the current state of the shared interrupt
sources.
Self-Nesting of Core Interrupts
Interrupts that are “self-nested” can be interrupted by events at the same
priority level. When the
SNEN
bit of the
SYSCFG
register is set, self-nesting
of core interrupts is supported. Self-nesting is supported for any interrupt
level generated with the
RAISE
instruction, as well as for core level
interrupts.
As an example, assume that the
SNEN
bit is set and the processor is servic-
ing an interrupt generated by the
RAISE 14;
instruction. Once the
RETI
register has been saved to the stack within the service routine, a second
RAISE 14;
instruction would allow the processor to service the second
interrupt.