Analog Devices ADSP-BF53x Blackfin, Reference

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Memory Address Alignment
5-16 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
The address-modify operation modifies addresses in any Index and
Pointer register (
I[3:0]
,
P[5:0]
,
FP
,
SP
) without accessing memory. If the
Index register’s corresponding B- and L-registers are set up for circular
buffering, the address-modify operation performs the specified buffer
wraparound (if needed).
The syntax is similar to post-modify addressing (index += modifier). For
Index registers, an M-register is used as the modifier. For Pointer registers,
another P-register is used as the modifier.
Consider the example,
I1 += M2
;
This instruction adds
M2
to
I1
and updates
I1
with the new value.
Memory Address Alignment
The processor requires proper memory alignment to be maintained for the
data size being accessed. Unless exceptions are disabled, violations of
memory alignment cause an alignment exception. Some instructions—for
example, many of the Video ALU instructions—automatically disable
alignment exceptions because the data may not be properly aligned when
stored in memory. Alignment exceptions may be disabled by issuing the
DISALGNEXCPT
instruction in parallel with a load/store operation.
Normally, the memory system requires two address alignments:
• 32-bit word load/stores are accessed on four-byte boundaries,
meaning the two least significant bits of the address are b#00.
• 16-bit word load/stores are accessed on two-byte boundaries,
meaning the least significant bit of the address must be b#0.