Analog Devices ADSP-BF53x Blackfin, Reference

Page: 247 / 1042

ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-19
Memory
the Invalid bit of each cache line to the invalid state. To implement this
technique, additional MMRs (
ITEST_COMMAND
and
ITEST_DATA[1:0]
) are
available to allow arbitrary read/write of all the cache entries directly. This
method is explained in the next section.
For invalidating the complete instruction cache, a third method is avail-
able. By clearing the
IMC
bit in the
IMEM_CONTROL
register (see Figure 6-2,
“L1 Instruction Memory Control Register,” on page 6-7 ), all Valid bits in
the instruction cache are set to the invalid state. A second write to the
IMEM_CONTROL
register to set the
IMC
bit configures the instruction memory
as cache again. An
SSYNC
instruction should be run before invalidating the
cache and a
CSYNC
instruction should be inserted after each of these
operations.
Instruction Test Registers
The Instruction Test registers allow arbitrary read/write of all L1 cache
entries directly. They make it possible to initialize the instruction tag and
data arrays and to provide a mechanism for instruction cache test, initial-
ization, and debug.
When the Instruction Test Command register (
ITEST_COMMAND)
is used,
the L1 cache data or tag arrays are accessed, and data is transferred
through the Instruction Test Data registers (
ITEST_DATA[1:0])
. The
ITEST_DATAx
registers contain either the 64-bit data that the access is to
write to or the 64-bit data that was read during the access. The lower 32
bits are stored in the
ITEST_DATA[0]
register, and the upper 32 bits are
stored in the
ITEST_DATA[1]
register. When the tag arrays are accessed,
ITEST_DATA[0]
is used. Graphical representations of the
ITEST
registers
begin with Figure 6-6 on page 6-21 .