ADSP-BF53x/BF56x Blackfin Processor Programming Reference
I-9
Index
DAG1 misaligned access,
4-66
DAG1 multiple CPLB hits,
4-66
DAG1 port preference (PORT_PREF1)
bit,
6-24
,
6-25
DAG1 protection violation,
4-66
DAG (data address generator) register
addressing modes,
5-18
as processor section (table),
C-3
defined,
1-14
,
2-6
description summary,
C-3
exceptions,
4-65
performance with reads,
6-26
register modification,
5-15
registers,
5-8
stalls,
4-9
support for branches,
4-3
dagreg, syntax,
9-3
data
flow,
2-1
memory stalls,
4-9
store format,
6-75
transfers,
2-8
watchpoints,
21-3
data, sign extending,
2-12
data, zero extending,
2-12
data[15:0] field,
6-23
,
6-42
data[31:16] field,
6-23
,
6-42
data[47:32] field,
6-22
,
6-41
data[63:48] field,
6-22
,
6-41
data address generator (DAG). See DAG
data address registers, initialization,
5-4
data address (WPDA[31:16]) field,
21-11
data arithmetic unit, diagram,
1-2
data bank access bit,
6-40
data banks, configuration,
6-30
data cache
access,
6-33
control instructions,
6-37
flush instruction,
C-101
data cache
(continued)
invalidation,
6-38
L1 memory,
6-2
,
6-29
data cacheability protection lookaside
buffer enable (ENDCPLB) bit,
6-25
,
6-26
,
6-30
,
6-51
data cache line, states,
6-34
data cache line flush and invalidate
(FLUSHINV) instruction. See
FLUSHINV
data cache line invalidate instruction,
C-101
data cache lines, instructions,
17-1
data cache prefetch (PREFETCH)
instruction,
6-37
,
17-3
,
C-101
data cache select/address bit 14,
6-40
data fetch 1 (DF1),
4-7
data fetch 2 (DF2),
4-7
data formats,
2-4
to
2-5
binary multiplication,
D-5
table,
2-13
data/instruction access bit,
6-40
data memory, L1,
6-24
to
6-38
data memory control
(DMEM_CONTROL) register,
6-24
,
6-47
data operations, CPLB,
6-47
data register file,
2-1
,
2-2
,
2-6
,
2-7
,
2-8
data registers
description,
1-13
,
C-2
groups,
2-6
names,
3-4
data SRAM, L1,
6-27
data test command
(DTEST_COMMAND) register,
6-39
data test data (DTEST_DATAx) registers,
6-41
,
6-42
,
17-2
data test registers,
6-38
to
6-42
data types,
2-11
to
2-23
Summary of Contents for ADSP-BF53x Blackfin
Page 38: ...Conventions xxxviii ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 134: ...System Reset and Powerup 3 18 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 324: ...Instruction Overview 7 20 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 486: ...Instruction Overview 13 28 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 512: ...Instruction Overview 14 26 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 604: ...Instruction Overview 15 92 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 688: ...Instruction Overview 18 48 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 742: ...Instruction Overview 19 54 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 752: ...Examples 20 10 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 790: ...ADSP BF535 Flags A 10 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 800: ...Performance Monitor Registers B 10 ADSP BF53x BF56x Blackfin Processor Programming Reference...
Page 1042: ...Index I 40 ADSP BF53x BF56x Blackfin Processor Programming Reference...