Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
12-12 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Modified Type I LFSR (without feedback)
Two instructions support the
LSFR
with no feedback.
Dreg_lo = CC = BXORSHIFT(A0, dreg )
Dreg_lo = CC = BXOR(A0, dreg )
In the first instruction the Accumulator
A0
is left-shifted by 1 prior to the
XOR reduction. This instruction provides a bit-wise XOR of
A0
logically
AND’ed with a
dreg
. The result of the operation is placed into both the
CC
flag and the least significant bit of the destination register. The operation
is shown in
Figure 12-2 .
The upper 15 bits of
dreg_lo
are overwritten with zero, and dr[0] = IN
after the operation.
Figure 12-2. A0 Left-Shifted by 1 Followed by XOR Reduction
A0[39] A0[38] A0[37] A0[0]
0
A0[39:0]
Left Shift by 1
Before XOR Reduction
D[31]
0
XOR Reduction
+ + + +
CC dreg_lo
IN
D[2] D[1] D[0]
A0[1] A0[0]
0
A0[30]
A0[38]
dr[15] dr[14] dr[13]
IN
dreg_lo[15:0]
After Operation