Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference C-5
Instruction Opcodes
This appendix uses the following conventions to describe options in the
assembler syntax:
• When there is a choice of any one register within a register group,
this appendix shows the register set using a single dash to indicate
the range of possible register numbers. The register numbers always
decrement from high to low. For example, “R7–0” means that any
one of the eight Data Registers can be used.
• A range of sequential registers or bits, considered as a group, are
denoted using a colon “:”. The register or bit numbers appear high-
est first, followed by the lowest. For example, the group of Data
Registers R3, R2, R1, and R0 are abbreviated R3:0. This nomen-
clature is similar to that used for valid Data Register pairs, but
here, more than a single pair can be represented. Another example
is the least significant eight bits of a register are denoted 7:0. In the
case of bits, there is no convention to include the register name
with the bit range; the register must be clear by context.
• Immediate values are designated as “
imm
” with the following
modifiers:
• “imm” indicates a signed value; for example,
imm7
.
• the “u” prefix indicates an unsigned value; for example,
uimm4.
• the decimal number indicates how many bits the value can
include; for example, imm5 is a 5-bit value.
• any alignment requirements are designated by an optional
“m” suffix followed by a number; for example, uimm16m2
is an unsigned, 16-bit integer that must be an even number,
and imm7m4 is a signed, 7-bit integer that must be a multi-
ple of 4.