Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 3-15
Operating Modes and States
After either the watchdog or System Software reset is initiated, the proces-
sor ensures that all asynchronous peripherals have recognized and
completed a reset.
For a reset generated by the watchdog timer, the processors transitions
into the Boot mode sequence. The Boot mode is configured by the state of
the
BMODE
and the No Boot on Software Reset control bits.
If the No Boot on Software Reset bit in
SYSCR
is cleared, the reset
sequence is determined by the
BMODE
control bits.
SWRST Register
A software reset can be initiated by setting the System Software Reset field
in the Software Reset register (
SWRST
). Bit 15 indicates whether a software
reset has occurred since the last time
SWRST
was read. Bit 14 and Bit 13,
respectively, indicate whether the Software Watchdog Timer or a Core
Double Fault has generated a software reset. Bits [15:13] are read-only
and cleared when the register is read. Bits [3:0] are read/write.
When the
BMODE
pins are not set to b#00 and the No Boot on Software
Reset bit in
SYSCR
is set, the processor starts executing from the start of
on-chip L1 memory. In this configuration, the core begins fetching
instructions from the beginning of on-chip L1 memory.
When the
BMODE
pins are set to b#00 the core begins fetching instructions
from address 0x2000 0000 (the beginning of ASYNC Bank 0).