Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
8-46 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
The indirect address and offset must yield an even number to maintain
2-byte half-word address alignment. Failure to maintain proper alignment
causes a misaligned memory access exception.
L
The instruction versions that explicitly modify
Ireg
support
optional circular buffering. See “Automatic Circular Addressing”
on page 1-21 for more details. Unless circular buffering is desired,
disable it prior to issuing this instruction by clearing the Length
Register (
Lreg
) corresponding to the
Ireg
used in this instruction.
Example: If you use
I2
to increment your address pointer, first
clear
L2
to disable circular buffering. Failure to explicitly clear
Lreg
beforehand can result in unexpected Ireg values.
The circular address buffer registers (Index, Length, and Base) are
not initialized automatically by Reset. Traditionally, user software
clears all the circular address buffer registers during boot-up to dis-
able circular buffering, then initializes them later, if needed.
Options
The Store High Data Register Half instruction supports the following
options.
• Post-increment the destination pointer I-register by 2 bytes.
• Post-decrement the destination pointer I-register by 2 bytes.