Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
14-16 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Four versions of the Logical Shift instruction support pointer shifting.
The instruction does not implicitly modify the input
src_pntr
value. For
the P-register versions of this instruction,
dest_pntr
can be the same
P-register as
src_pntr
. Doing so explicitly modifies the source register.
The rest of this description applies to the data shift versions of this
instruction relating to D-registers and Accumulators.
The Logical Shift instruction supports 16-bit and 32-bit instruction
length.
• The “
>>=
” and “
<<=
” syntax instruction is 16 bits in length, allow-
ing for smaller code at the expense of flexibility.
• The “
>>
”, “
<<
”, and “
LSHIFT
” syntax instruction is 32 bits in
length, providing a separate source and destination register, alter-
native data sizes, and parallel issue with Load/Store instructions.
Both syntaxes support constant and registered shift magnitudes.
For the
LSHIFT
version, the sign of the shift magnitude determines the
direction of the shift.
• Positive shift magnitudes produce Left shifts.
• Negative shift magnitudes produce Right shifts.
Table 14-2. Logical Shifts
Syntax Description
“>>=”
and “<<=” The value in dest_reg is shifted by the number of places specified by
shift_magnitude. The data size is always 32 bits long. The entire 32 bits
of the shift_magnitude determine the shift value. Shift magnitudes larger
than 0x1F produce a 0x00000000 result.
“>>”, “<<”,
and “LSHIFT” The value in src_reg is shifted by the number of places specified in
shift_magnitude, and the result is stored into dest_reg.
The LSHIFT versions can shift 32-bit Dreg and 40-bit Accumulator reg-
isters by up to –32 t31 places.