Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 3-7
Operating Modes and States
Supervisor Mode
The processor services all interrupt, NMI, and exception events in Super-
visor mode.
Supervisor mode has full, unrestricted access to all processor system
resources, including all emulation resources, unless a CPLB has been con-
figured and enabled. See
“Memory Management Unit” on page 6-45 for a
further description. Only Supervisor mode can use the register alias
USP
,
which references the User Stack Pointer in memory. This register alias is
necessary because in Supervisor mode,
SP
refers to the kernel stack pointer
rather than to the user stack pointer.
Normal processing begins in Supervisor mode from the Reset state. Deas-
serting the
RESET
signal switches the processor from the Reset state to
Supervisor mode where it remains until an emulation event or Return
instruction occurs to change the mode. Before the Return instruction is
issued, the
RETI
register must be loaded with a valid return address.
Non-OS Environments
For non-OS environments, application code should remain in Supervisor
mode so that it can access all core and system resources. When
RESET
is
deasserted, the processor initiates operation by servicing the reset event.
Emulation is the only event that can pre-empt this activity. Therefore,
lower priority events cannot be processed.
One way of keeping the processor in Supervisor mode and still allowing
lower priority events to be processed is to set up and force the lowest pri-
ority interrupt (
IVG15
). Events and interrupts are described further in
“Events and Interrupts” on page 4-29 . After the low priority interrupt has
been forced using the
RAISE 15
instruction,
RETI
can be loaded with a
return address that points to user code that can execute until
IVG15
is
issued. After
RETI
has been loaded, the
RTI
instruction can be issued to
return from the reset event.