Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 15-59
Arithmetic Operations
opt_mode
: Optionally
(FU)
,
(IS)
,
(IU)
,
(T)
,
(TFU)
,
(S2RND)
,
(ISS2)
or
(IH)
. Optionally,
(M)
can be used with MAC1 versions either alone or
with any of these other options. If multiple options are specified together
for a MAC, the options must be separated by commas and enclosed within
a single set of parentheses. Example:
(M, TFU)
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Multiply and Multiply-Accumulate to Half-Register instruction mul-
tiplies two 16-bit half-word operands. The instruction stores, adds or
subtracts the product into a designated Accumulator. It then copies 16
bits (saturated at 16 bits) of the Accumulator into a data half-register.
The fraction versions of this instruction (the default and “
(FU)
” options)
transfer the Accumulator result to the destination register according to the
diagrams in
Figure 15-1 .
The integer versions of this instruction (the “
(IS)
” and “
(IU)
” options)
transfer the Accumulator result to the destination register according to the
diagrams in
Figure 15-2 .
The Multiply-and-Accumulate Unit 0 (MAC0) portion of the architecture
performs operations that involve Accumulator
A0
and loads the results
into the lower half of the destination data register. MAC1 performs
A1
operations and loads the results into the upper half of the destination data
register.
All versions of this instruction that support rounding are affected by the
RND_MOD
bit in the
ASTAT
register when they copy the results into the desti-
nation register.
RND_MOD
determines whether biased or unbiased rounding
is used.