Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 7-15
Program Flow Control
Functional Description
The Zero-Overhead Loop Setup instruction provides a flexible,
counter-based, hardware loop mechanism that provides efficient,
zero-overhead software loops. In this context, zero-overhead means that
the software in the loops does not incur a performance or code size penalty
by decrementing a counter, evaluating a loop condition, then calculating
and branching to a new target address.
L
When the
Begin_Loop
address is the next sequential address after
the
LSETUP
instruction, the loop has zero overhead. If the
Begin_Loop
address is not the next sequential address after the
LSETUP
instruction, there is some overhead that is incurred on loop
entry only.
The architecture includes two sets of three registers each to support two
independent, nestable loops. The registers are
Loop_Top (LTn)
,
Loop_Bottom (LBn)
and
Loop_Count (LCn)
. Consequently,
LT0
,
LB0
, and
LC0
describe
Loop0
, and
LT1
,
LB1
, and
LC1
describe
Loop1
.
The
LOOP
and
LSETUP
instructions are a convenient way to initialize all
three registers in a single instruction. The size of the
LOOP
and
LSETUP
instructions only supports a finite number of bits, so the loop range is lim-
ited. However,
LT0
and
LT1
,
LB0
and
LB1
and
LC0
and
LC1
can be
initialized manually using Move instructions if loop length and repetition
count need to be beyond the limits supported by the
LOOP
and
LSETUP
syn-
tax. Thus, a single loop can span the entire 4 GB of memory space.
L
When initializing
LT0
and
LT1
,
LB0
and
LB1
, and
LC0
and
LC1
man-
ually, make sure that
Loop_Top
(
LTn
) and
Loop_Bottom
(
LBn
) are
configured before setting
Loop_Count
(
LCn
) to the desired loop
count value.
The instruction syntax supports an optional initialization value from a
P-register or P-register divided by 2.