Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 21-19
Debug
Listing 21-1. Recreating the Execution Trace in Memory
[--sp] = (r7:7, p5:2); /* save registers used in this routine */
p5 = 32; /* 32 reads are needed to empty TBUF */
p2.l = buf; /* pointer to the header (first location) of the
software trace buffer */
p2.h = buf; /* the header stores the first available empty buf
location for subsequent trace dumps */
p4 = [p2++]; /* get the first available empty buf location from
the buf header */
p3.l = TBUF & 0xffff; /* low 16 bits of TBUF */
p3.h = TBUF >> 16; /* high 16 bits of TBUF */
lsetup(loop1_start, loop1_end) lc0 = p5;
loop1_start: r7 = [p3]; /* read from TBUF */
loop1_end: [p4++] = r7; /* write to memory and increment */
[p2] = p4; /* pointer to the next available buf location is
saved in the header of buf */
(r7:7, p5:3) = [sp++]; /* restore saved registers */
Performance Monitoring Unit
Two 32-bit counters, the Performance Monitor Counter registers
(
PFCNTR[1:0]
) and the Performance Control register (
PFCTL
), count the
number of occurrences of an event from within a processor core unit dur-
ing a performance monitoring period. These registers provide feedback
indicating the measure of load balancing between the various resources on
the chip so that expected and actual usage can be compared and analyzed.
In addition, events such as mispredictions and hold cycles can also be
monitored.