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ADSP-BF53x/BF56x Blackfin Processor Programming Reference

3-3

Operating Modes and States

User Mode

The processor is in User mode when it is not in Reset or Idle state, and
when it is not servicing an interrupt, NMI, exception, or emulation event.
User mode is used to process application level code that does not require
explicit access to system registers. Any attempt to access restricted system
registers causes an exception event. Table 3-2 lists the registers that may
be accessed in User mode.

Figure 3-1. Processor Modes and States

Interrupt

RTI,

Event

EMULATION

SUPERVISOR

IDLE

RESET

Application
Level Code

System Code,
Event Handlers

USER

Emulation

Event

Emulation

RTX, RTN

Exception

RTE

RST Inactive

Emulation Event (1)

(1) Normal exit from Reset is to Supervisor mode. However, emulation hardware may
have initiated a reset. If so, exit from Reset is to Emulation.

RST

Active

IDLE
instruction

or

IDLE instruction

Wakeup

RTE

Interrupt

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Summary of Contents for ADSP-BF53x Blackfin

Page 1: ...a ADSP BF53x BF56x Blackfin Processor Programming Reference Revision 1 2 February 2007 Part Number 82 000556 01 Analog Devices Inc One Technology Way Norwood Mass 02062 9106...

Page 2: ...to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No lic...

Page 3: ...New in This Manual xxvii Technical or Customer Support xxviii Supported Processors xxix Product Information xxix MyAnalog com xxx Processor Product Information xxx Related Documents xxxi Online Techni...

Page 4: ...ets xxxv Conventions xxxvi INTRODUCTION Core Architecture 1 1 Memory Architecture 1 4 Internal Memory 1 5 External Memory 1 6 I O Memory Space 1 6 Event Handling 1 6 Core Event Controller CEC 1 8 Syst...

Page 5: ...19 Automatic Circular Addressing 1 21 COMPUTATIONAL UNITS Using Data Formats 2 4 Binary String 2 4 Unsigned 2 4 Signed Numbers Two s Complement 2 5 Fractional Representation 1 15 2 5 Register Files 2...

Page 6: ...Logic Unit ALU 2 26 ALU Operations 2 26 Single 16 Bit Operations 2 27 Dual 16 Bit Operations 2 27 Quad 16 Bit Operations 2 28 Single 32 Bit Operations 2 29 Dual 32 Bit Operations 2 29 ALU Instruction...

Page 7: ...Shifter 2 48 Shifter Operations 2 48 Two Operand Shifts 2 49 Immediate Shifts 2 49 Register Shifts 2 50 Three Operand Shifts 2 50 Immediate Shifts 2 50 Register Shifts 2 51 Bit Test Set Clear Toggle...

Page 8: ...State 3 10 Reset State 3 10 System Reset and Powerup 3 12 Hardware Reset 3 13 SYSCR Register 3 14 Software Resets and Watchdog Timer 3 14 SWRST Register 3 15 Core Only Software Reset 3 16 Core and Sys...

Page 9: ...imensional Loops 4 24 Loop Unrolling 4 26 Saving and Resuming Loops 4 27 Example Code for Using Hardware Loops in an ISR 4 28 Events and Interrupts 4 29 System Interrupt Processing 4 31 System Periphe...

Page 10: ...pt 4 47 Core Timer Interrupt 4 47 General purpose Interrupts IVG7 IVG15 4 47 Interrupt Processing 4 48 Global Enabling Disabling of Interrupts 4 48 Servicing Interrupts 4 48 Software Interrupts 4 50 N...

Page 11: ...ceptions and the Pipeline 4 67 Deferring Exception Processing 4 68 Example Code for an Exception Handler 4 68 Example Code for an Exception Routine 4 70 ADDRESS ARITHMETIC UNIT Addressing With the AAU...

Page 12: ...rview of On Chip Level 1 L1 Memory 6 2 Overview of Scratchpad Data SRAM 6 4 Overview of On Chip Level 2 L2 Memory 6 4 L1 Instruction Memory 6 5 IMEM_CONTROL Register 6 5 L1 Instruction SRAM 6 7 L1 Ins...

Page 13: ...r 6 24 L1 Data SRAM 6 27 L1 Data Cache 6 29 Example of Mapping Cacheable Address Space 6 30 Data Cache Access 6 33 Cache Write Method 6 35 IPRIO Register and Write Buffer Depth 6 35 Data Cache Control...

Page 14: ...ns 6 54 ICPLB_DATAx Registers 6 55 DCPLB_DATAx Registers 6 57 DCPLB_ADDRx Registers 6 59 ICPLB_ADDRx Registers 6 60 DCPLB_STATUS and ICPLB_STATUS Registers 6 61 DCPLB_FAULT_ADDR and ICPLB_FAULT_ADDR R...

Page 15: ...5 Call 7 8 RTS RTI RTX RTN RTE Return 7 10 LSETUP LOOP 7 13 LOAD STORE Load Immediate 8 3 Load Pointer Register 8 7 Load Data Register 8 10 Load Half Word Zero Extended 8 15 Load Half Word Sign Extend...

Page 16: ...l Word Zero Extended 9 10 Move Half to Full Word Sign Extended 9 13 Move Register Half 9 15 Move Byte Zero Extended 9 23 Move Byte Sign Extended 9 25 STACK CONTROL SP Push 10 2 SP Push Multiple 10 5 S...

Page 17: ...ent 12 4 OR 12 6 Exclusive OR 12 8 BXORSHIFT BXOR 12 10 BIT OPERATIONS BITCLR 13 2 BITSET 13 4 BITTGL 13 6 BITTST 13 8 DEPOSIT 13 10 EXTRACT 13 16 BITMUX 13 21 ONES One s Population Count 13 26 SHIFT...

Page 18: ...ADJ 15 26 MAX 15 30 MIN 15 32 Modify Decrement 15 34 Modify Increment 15 37 Multiply 16 Bit Operands 15 43 Multiply 32 Bit Operands 15 51 Multiply and Multiply Accumulate to Accumulator 15 53 Multiply...

Page 19: ...Interrupts 16 15 RAISE Force Interrupt Reset 16 17 EXCPT Force Exception 16 20 Test and Set Byte Atomic 16 22 No Op 16 25 CACHE CONTROL PREFETCH 17 3 FLUSH 17 5 FLUSHINV 17 7 IFLUSH 17 9 VIDEO PIXEL O...

Page 20: ...VECTOR OPERATIONS Add on Sign 19 3 VIT_MAX Compare Select 19 8 Vector ABS 19 15 Vector Add Subtract 19 18 Vector Arithmetic Shift 19 23 Vector Logical Shift 19 28 Vector MAX 19 32 Vector MIN 19 35 Vec...

Page 21: ...isters 21 6 WPIACTL Register 21 7 Data Address Watchpoints 21 10 WPDAn Registers 21 10 WPDACNTn Registers 21 11 WPDACTL Register 21 12 WPSTAT Register 21 14 Trace Unit 21 15 TBUFCTL Register 21 16 TBU...

Page 22: ...perating Modes and States A 1 ADSP BF535 Flags A 2 CORE MMR ASSIGNMENTS L1 Data Memory Controller Registers B 1 L1 Instruction Memory Controller Registers B 4 Interrupt Controller Registers B 6 Debug...

Page 23: ...13 Load Store Instructions C 16 Move Instructions C 28 Stack Control Instructions C 37 Control Code Bit Management Instructions C 39 Logical Operations Instructions C 43 Bit Operations Instructions C...

Page 24: ...in Processor Programming Reference NUMERIC FORMATS Unsigned or Signed Two s complement Format D 1 Integer or Fractional Data Formats D 1 Binary Multiplication D 5 Fractional Mode And Integer Mode D 6...

Page 25: ...this are noted in Chapter 6 Memory The manual provides information on how assembly instructions execute on the Blackfin processor s architecture along with reference information about processor opera...

Page 26: ...ibes Idle state and Reset state Chapter 4 Program Sequencer Describes the operation of the program sequencer which controls program flow by providing the address of the next instruction to be executed...

Page 27: ...ADSP BF535 Considerations Provides a description of the status flag bits for the ADSP BF535 processor only Appendix B Core MMR Assignments Lists the core memory mapped registers their addresses and cr...

Page 28: ...analog com processors manuals E mail tools questions to processor tools support analog com E mail processor questions to processor support analog com World wide support processor europe analog com Eur...

Page 29: ...amily of high performance 32 bit floating point processors that can be used in speech sound graphics and imaging applications VisualDSP currently supports the following SHARC families ADSP 2106x ADSP...

Page 30: ...e mail notifications containing updates to the Web pages that meet your interests MyAnalog com provides access to books application notes data sheets code examples and more Registration Visit www myan...

Page 31: ...FTP Web site at ftp ftp analog com or ftp 137 71 25 69 ftp ftp analog com Related Documents The following publications that describe the ADSP BF53x BF56x proces sors and related processors can be orde...

Page 32: ...nd Preprocessor Manual VisualDSP Linker and Utilities Manual VisualDSP Kernel VDK User s Guide Visit the Technical Library Web site to access all processor and tools manuals and data sheets http www a...

Page 33: ...and Index commands Open online Help from context sensitive user interface items tool bar buttons menu commands and windows Accessing Documentation From Windows In addition to any shortcuts you may ha...

Page 34: ...the Windows Start Button Access VisualDSP online Help by clicking the Start button and choosing Programs Analog Devices VisualDSP and VisualDSP Documentation Access the PDF files by clicking the Start...

Page 35: ...e reference and instruction set reference manuals may be ordered through the Literature Center at 1 800 ANALOGD 1 800 262 5643 or downloaded from the Analog Devices Web site Manuals may be ordered by...

Page 36: ...keywords and feature names are in text with letter gothic font filename Non keyword placeholders appear in text with italic style format SWRST Software Reset register Register names appear in UPPERCA...

Page 37: ...related topic In the online version of this book the word Note appears instead of this symbol Caution Incorrect device operation may result if Caution Device damage may result if A Caution identifies...

Page 38: ...Conventions xxxviii ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 39: ...th on chip L2 memory have slightly different system interfaces Differences and commonalities at a global level are discussed in Chapter 6 Memory For a full description of the system architecture beyon...

Page 40: ...ns come from the multiported register file and instruction constant fields Figure 1 1 Processor Core Architecture SEQUENCER ALIGN DECODE LOOP BUFFER 16 16 8 8 8 8 40 40 A0 A1 BARREL SHIFTER DATA ARITH...

Page 41: ...ions two 16 bit ALU operations can be performed simultaneously on register pairs a 16 bit high half and 16 bit low half of a compute register By also using the second ALU quad 16 bit operations are po...

Page 42: ...access to a subset of system resources thus providing a protected software environment Supervisor and Emula tion modes have unrestricted access to the system and core resources The Blackfin processor...

Page 43: ...nternal memory and the external memory spaces Internal Memory At a minimum each Blackfin processors has three blocks of on chip mem ory that provide high bandwidth access to the core L1 instruction me...

Page 44: ...if each is fully populated with 1M byte of memory I O Memory Space Blackfin processors do not define a separate I O space All resources are mapped through the flat 32 bit address space Control regist...

Page 45: ...hronous to program flow That is the exception is taken before the instruction is allowed to complete Conditions such as data alignment violations and undefined instructions cause exceptions Interrupts...

Page 46: ...heral interrupt sources to the prioritized gen eral purpose interrupt inputs of the CEC Although the processor provides a default mapping the user can alter the mappings and priorities of interrupt ev...

Page 47: ...edded spaces Tokens include numbers register names keywords user identifiers and also some multicharacter special symbols like or Instruction Delimiting A semicolon must terminate every instruction Se...

Page 48: ...n a general comment it issues an assembler warning A comment functions as white space Notation Conventions This manual and the assembler use the following conventions Register names are alphabetical f...

Page 49: ...gister names are reserved and may not be used as program identifiers This manual uses the following conventions When there is a choice of any one register within a register group this manual shows the...

Page 50: ...integer that must be an even number Loop PC relative signed values are designated as lppcrel with the following modifiers the decimal number indicates how many bits the value can include for example...

Page 51: ...sters R0 R1 R2 R3 R4 R5 R6 and R7 that normally contain data for manipulation Abbreviated D register or Dreg Data Registers can be accessed as 32 bit registers or optionally as two independent 16 bit...

Page 52: ...eg Clear Lreg to disable circular addressing for the corresponding Ireg Example Clear L3 to disable circular addressing for I3 Base Registers The set of 32 bit registers B0 B1 B2 B3 that normally cont...

Page 53: ...e architecture Table 1 3 Arithmetic Status Flag Summary Flag Description AC0 Carry ALU0 AC0_COPY Carry ALU0 copy AC1 Carry ALU1 AN Negative AQ Quotient AV0 Accumulator 0 Overflow AVS0 Accumulator 0 St...

Page 54: ...In DSP instructions that assume placement of a binal point for example in computing sign bits for normalization or for alignment purposes the binal point convention depends on the size of the registe...

Page 55: ...n hold with the same sign as the original If an operation would otherwise cause a positive value to overflow and become negative instead saturation limits the result to the maximum positive value for...

Page 56: ...h saturation however a left shift of 3 or more places would always produce the largest positive 16 bit number 0x7FFF decimal 32 767 Another common example is copying the lower half of a 32 bit registe...

Page 57: ...ew number will have only M bits of precision where N M so N M bits of precision are removed from the number in the process of rounding The round to nearest method returns the closest number to the ori...

Page 58: ...e significant bits representing a number is to simply mask off the N M lower bits This process is known as trunca tion and results in a relatively large bias Figure 1 3 shows other examples of roundin...

Page 59: ...L register must be an unsigned number with magnitude less than 231 The magnitude of the modifier should be less than the length of the circular buffer The initial location of the pointer I should be w...

Page 60: ...ify Decrement instructions Such instructions are still affected by circular addressing if enabled Disable circular addressing for an Ireg by clearing the Lreg that corre sponds to the Ireg used in the...

Page 61: ...shifter executes logical shifts and arithmetic shifts and performs bit packing and extraction The video ALUs perform Single Instruction Multiple Data SIMD logical operations on specific 8 bit data op...

Page 62: ...uctions have unrestricted access to the data registers in the Data Register File Multifunction opera tions may have restrictions that are described in the section for that particular operation Two add...

Page 63: ...UFFER 16 16 8 8 8 8 40 40 A0 A1 BARREL SHIFTER DATA ARITHMETIC UNIT CONTROL UNIT R7 H R6 H R5 H R4 H R3 H R2 H R1 H R0 H R7 L R6 L R5 L R4 L R3 L R2 L R1 H R0 L ASTAT 40 40 32 32 32 32 32 32 32 LD0 LD...

Page 64: ...sor family arithmetic signed numbers are always in two s complement format These processors do not use signed magnitude one s complement binary coded decimal BCD or excess n formats Binary String The...

Page 65: ...tic is optimized for numerical values in a fractional binary format denoted by 1 15 one dot fifteen In the 1 15 format 1 sign bit the Most Significant Bit MSB and 15 fractional bits represent values f...

Page 66: ...r addressing operations The DAG registers are dedicated registers that manage zero over head circular buffers for DSP operations For more information on Pointer and DAG registers see Chapter 5 Address...

Page 67: ...bit register R0 may be regarded as two independent register halves R0 L and R0 H For example these instructions represent a 32 bit and a 16 bit operation R2 R1 R2 32 bit addition R2 L R1 H R0 L 16 bi...

Page 68: ...ocessor has two dedicated 40 bit accumulator registers called A0 and A1 Each can be referred to as its 16 bit low half An L or high half An H plus its 8 bit extension An X Each can also be referred to...

Page 69: ...e register Sysreg denotes the system registers ASTAT SEQSTAT SYSCFG RETI RETX RETN RETE or RETS LC 1 0 LT 1 0 LB 1 0 CYCLES and CYCLES2 Preg denotes any Pointer register FP or SP register Dreg_even de...

Page 70: ...the instruction Indicates the flag is cleared Indicates no effect Table 2 1 Register File Instruction Summary Instruction ASTAT Status Flags AZ AN AC0 AC0_COPY AC1 AV0 AVS AV1 AV1S CC V V_COPY VS all...

Page 71: ...s for data that resides in memory in the register file and in the accumulators In the table the letter d represents one bit and the letter s represents one signed bit An H Dreg_hi Dreg_lo A0 Dreg_hi A...

Page 72: ...tions sign extend signed 16 bit half words and 8 bit bytes Other instructions manipulate data as 32 bit numbers In addition two 16 bit half words or four 8 bit bytes can be manipulated as 32 bit value...

Page 73: ...d dddd 16 0 Unsigned Half Word dddd dddd dddd dddd 0000 0000 0000 0000 dddd dddd dddd dddd 16 0 Signed Half Word sddd dddd dddd dddd ssss ssss ssss ssss sddd dddd dddd dddd 8 0 Unsigned Byte dddd dddd...

Page 74: ...s is set if the Most Signifi cant Bit MSB changes in a manner not predicted by the signs of the operands and the nature of the operation For example adding two posi tive numbers must generate a positi...

Page 75: ...t to be in 1 31 format which can be rounded to 1 15 format The resulting format appears in Figure 2 5 on page 2 18 In the integer mode the left shift does not occur For example if the oper ands are in...

Page 76: ...unsigned Interpret flags Subtraction Signed or unsigned Interpret flags Logical Binary string Same as operands Division Explicitly signed or unsigned Same as operands Table 2 4 Multiplier Fractional...

Page 77: ...s up with bit 1 of A0 which is bit 1 of A0 W The Least Significant Bit LSB is zero filled The fractional multiplier result format appears in Figure 2 5 For integer arithmetic the 32 bit product regist...

Page 78: ...od uct with the current contents of the A0 or A1 register to produce the final 40 bit result Figure 2 5 Fractional Multiplier Results Format 31 31 31 31 31 31 31 31 31 30 29 28 27 26 25 24 23 22 21 20...

Page 79: ...f precision whereas the new number will have only M bits of precision where N M The process of rounding then removes N M bits of precision from the number The RND_MOD bit in the ASTAT register determi...

Page 80: ...ry between bit 15 and bit 16 Rounding can be specified as part of the instruction code When rounding is selected the output regis ter contains the rounded 16 bit result the accumulator is never rounde...

Page 81: ...16 is forced to 0 This algorithm is employed on every rounding operation but is evident only when the bit patterns shown in the lower 16 bits of the next example are present Figure 2 7 Typical Unbias...

Page 82: ...o s complement fraction this method returns 0 5 binary 0 1 The original fraction lies exactly midway between 0 5 and 0 0 binary 0 0 so this method rounds up Because it always rounds up this method is...

Page 83: ...rations work normally This mode allows more efficient implementation of bit specified algorithms that use biased rounding for example the Global System for Mobile Communica tions GSM speech compressio...

Page 84: ...tion of two 32 bit numbers biased rounding at bit 12 depositing the result in a half word R3 L R4 R5 RND20 performs an addition of two 32 bit numbers biased rounding at bit 20 depositing the result in...

Page 85: ...version of AV1 AV1S Sticky A1 Overflow 0 Last result written from ALU to Data Register File register has not overflowed 1 Last result has overflowed V Dreg Overflow Sticky version of V AN Negative Re...

Page 86: ...cal AND OR NOT XOR bitwise XOR Negate Functions ABS MAX MIN Round division primitives ALU Operations Primary ALU operations occur on ALU0 while parallel operations occur on ALU1 which performs a subse...

Page 87: ...high half with no saturation Dual 16 Bit Operations In dual 16 bit operations any two 32 bit registers may be used as the input to the ALU considered as pairs of 16 bit operands An addition subtracti...

Page 88: ...t inputs are presented to ALU1 as to ALU0 The instruction construct is identical to that of a dual 16 bit operation and input operands must be the same for both ALUs For example R3 R0 R1 R2 R0 R1 S pe...

Page 89: ...registers P 5 0 SP FP L Instructions may not intermingle Pointer registers with Data registers For example R3 R1 R2 NS adds the 32 bit contents of R2 to the 32 bit contents of R1 and deposits the resu...

Page 90: ...differences of the A0 and A1 registers For example R3 A0 A1 R4 A0 A1 S transfers to the result registers two 32 bit saturated sum and difference values of the ALU registers ALU Instruction Summary Tab...

Page 91: ...bit register RND denotes rounding a half word RND12 denotes saturating the result of an addition or subtraction and rounding the result on bit 12 RND20 denotes saturating the result of an addition or...

Page 92: ...0S AV1 AV1S V V_COPY VS AQ Dreg Dreg Dreg Dreg Dreg Dreg S Dreg Dreg Dreg Dreg Dreg Dreg Dreg_lo_hi Dreg_lo_hi Dreg_lo_hi Dreg_lo_hi Dreg_lo_hi Dreg_lo_hi S Dreg Dreg Dreg Dreg Dreg Dreg Dreg Dreg Dre...

Page 93: ...n An An An An An An An An S An An S An An S Dreg_lo_hi Dreg RND Dreg_lo_hi Dreg Dreg RND12 Dreg_lo_hi Dreg Dreg RND12 Dreg_lo_hi Dreg Dreg RND20 Dreg_lo_hi Dreg Dreg RND20 Dreg_lo SIGNBITS Dreg Dreg_l...

Page 94: ...ction division algorithm The division can be either signed or unsigned but both the dividend and divisor must be of the same type Details about using division and pro gramming examples are available i...

Page 95: ...include Quad 8 Bit Add or Subtract Quad 8 Bit Average Quad 8 Bit Pack or Unpack Quad 8 Bit Subtract Absolute Accumulate Byte Align For more information about the operation of these instructions see Ch...

Page 96: ...ulator register A1 or A0 The accumulator results can be saturated to 32 or 40 bits The multiplier result can also be written directly to a 16 or 32 bit destination register with optional rounding Each...

Page 97: ...only in the A0 or A1 registers but also in a variety of 16 or 32 bit Data registers in the Data Register File Rounding or Saturating Multiplier Results On a multiply and accumulate operation the accum...

Page 98: ...ow or underflow has occurred If the bit is set 1 an overflow or underflow has occurred The AV0S and AV1S bits are sticky bits Bit 24 V and bit 25 VS are set if overflow occurs in extracting the accumu...

Page 99: ...n Summary Instruction ASTAT Status Flags AV0 AV0S AV1 AV1S V V_COPY VS Dreg_lo Dreg_lo_hi Dreg_lo_hi Dreg_hi Dreg_lo_hi Dreg_lo_hi Dreg Dreg_lo_hi Dreg_lo_hi An Dreg_lo_hi Dreg_lo_hi An Dreg_lo_hi Dre...

Page 100: ...ned fraction No shift correction is made IU Input data operands are unsigned integer No shift correction is made T Input data operands are signed fraction When copying to the destination half register...

Page 101: ...rands are signed fraction with no extension bits in the Accumulators at 32 bits Left shift correction of the product is performed as required This option is used for legacy GSM speech vocoder algorith...

Page 102: ...ble at the MAC inputs provid ing four 16 bit operands to chose from One of the operands must be selected from the low half or the high half of one 32 bit word The other operand must be selected from t...

Page 103: ...to a 40 bit adder subtracter which may add or subtract the new product from the contents of the Accumulator Result register or pass the new product directly to the Data Register File Results register...

Page 104: ...bits If a 16 bit destination register is a low half then MAC0 is used if it is a high half then MAC1 is used For a 32 bit desti nation register either MAC0 or MAC1 is used If the destination register...

Page 105: ...uction deposits the lower 16 bits of the multiply answer with any required saturation into the high half of R0 using MAC1 R0 R1 L R2 L Regardless of operand type the preceding operation deposits 32 bi...

Page 106: ...n takes multiple cycles to execute For more information about the exact operation of this instruction refer to Chapter 15 Arith metic Operations This macro function is interruptable and does not modif...

Page 107: ...s instruction represents two multiply and accumulate operations In one operation MAC1 the high half of R1 is multiplied by the low half of R2 and added to the contents of the A1 Accumulator In the sec...

Page 108: ...sferred to a register Either a 16 or 32 bit register may be speci fied as the destination register Barrel Shifter Shifter The shifter provides bitwise shifting functions for 16 32 or 40 bit inputs yie...

Page 109: ...hmetic shift logical shift and rotate instructions can obtain the shift argument from a register or directly from an immediate value in the instruction For details about shifter related instructions s...

Page 110: ...hift value and when the magnitude of the shift is greater than or equal to 32 then the result is either 0 or 1 The following example shows the input value upshifted R0 contains 0000 B6A3 R2 contains 0...

Page 111: ...R0 L 0x04 results in R1 H contains 6A30 Register Shifts Register based shifts use a register to hold the shift value When a register is used to hold the shift value for ASHIFT LSHIFT or ROT then the...

Page 112: ...he method to test set clear and toggle specific bits of a data register All instructions have two arguments the source register and the bit field value The test instruction does not change the source...

Page 113: ...ags see Chapter 14 Shift Rotate Operations In Table 2 11 note the meaning of these symbols Dreg denotes any Data Register File register Dreg_lo denotes the lower 16 bits of any Data Register File regi...

Page 114: ...V0 AV0S AV1 AV1S CC V V_COPY VS BITCLR Dreg uimm5 BITSET Dreg uimm5 BITTGL Dreg uimm5 CC BITTST Dreg uimm5 CC BITTST Dreg uimm5 Dreg DEPOSIT Dreg Dreg Dreg EXTRACT Dreg Dreg BITMUX Dreg Dreg A0 Dreg_l...

Page 115: ..._hi uimm4 Dreg_lo_hi Dreg_lo_hi uimm4 Dreg Dreg Dreg Dreg Dreg Dreg Dreg ASHIFT Dreg BY Dreg_lo Dreg LSHIFT Dreg BY Dreg_lo Dreg ROT Dreg BY imm6 Dreg ASHIFT Dreg BY Dreg_lo V Dreg LSHIFT Dreg BY Dreg...

Page 116: ...amming Reference Dreg_lo_hi LSHIFT Dreg_lo_hi BY Dreg_lo An An ASHIFT BY Dreg _lo 0 1 An An ROT BY imm6 Dreg Dreg Dreg 1 Dreg Dreg Dreg 2 Table 2 11 Shifter Instruction Summary Cont d Instruction ASTA...

Page 117: ...domain of application programs Supervisor mode and Emulation mode are usually reserved for the kernel code of an operating system The processor mode is determined by the Event Controller When servic i...

Page 118: ...IPEND 0 IPEND 1 IPEND 2 and IPEND 3 0 Exception Supervisor 0x08 The core is processing an exception event if IPEND 0 0 IPEND 1 0 IPEND 2 0 IPEND 3 1 and IPEND 15 4 are 0 s or 1 s NMI Supervisor 0x04...

Page 119: ...t to access restricted system registers causes an exception event Table 3 2 lists the registers that may be accessed in User mode Figure 3 1 Processor Modes and States Interrupt RTI Event EMULATION SU...

Page 120: ...appears in Table 3 3 Any attempt to issue any of the protected instructions from User mode causes an exception event Table 3 2 Registers Accessible in User Mode Processor Registers Register Names Dat...

Page 121: ...ss must be loaded into the RETI register Second an RTI must be issued The following example code shows how to enter User mode upon reset Example Code to Enter User Mode Upon Reset Listing 3 1 provides...

Page 122: ...errupt service routine becomes non interruptible because the return address is not saved on the stack The processor remains in User mode until one of these events occurs An interrupt NMI or exception...

Page 123: ...ulation event or Return instruction occurs to change the mode Before the Return instruction is issued the RETI register must be loaded with a valid return address Non OS Environments For non OS enviro...

Page 124: ...can be processed Example Code for Supervisor Mode Coming Out of Reset To remain in Supervisor mode when coming out of the Reset state use code as shown in Listing 3 2 Listing 3 2 Staying in Superviso...

Page 125: ...Emulation mode until the emulation service routine executes an RTE instruction If no interrupts are pending when the RTE instruction executes the processor switches to User mode Otherwise the process...

Page 126: ...n with the WAKEUP signal When the WAKEUP signal is asserted the processor wakes up and the STI instruction enables interrupts again Example Code for Transition to Idle State To transition to the Idle...

Page 127: ...tion of Reset State Core Operating Mode Supervisor mode in reset event clocks stopped Rounding Mode Unbiased rounding Cycle Counters Disabled zero DAG Registers I L B M Random values must be cleared a...

Page 128: ...tion see SYSCR Register on page 3 14 System Software Reset Writing b 111 to bits 2 0 in the system MMR SWRST at address 0xFFC0 0100 causes a System Soft ware reset Resets only the peripherals excludin...

Page 129: ...strapped by tying them directly to either VDD or VSS The pins and the corresponding bits in SYSCR configure the Boot mode that is employed after hardware reset or Core Double Fault Reset If the core e...

Page 130: ...e destinations from SYSCR Refer to the Reset and Booting chapter of your Blackfin Processor Hardware Reference for details Software Resets and Watchdog Timer A software reset may be initiated in three...

Page 131: ...t can be initiated by setting the System Software Reset field in the Software Reset register SWRST Bit 15 indicates whether a software reset has occurred since the last time SWRST was read Bit 14 and...

Page 132: ...eriod Core and System Reset To perform a system and core reset use the code sequence shown in Listing 3 4 Figure 3 2 Software Reset Register 0 Software Reset Register SWRST 15 14 13 12 11 10 9 8 7 6 5...

Page 133: ...eference 3 17 Operating Modes and States Listing 3 4 Core and System Reset Issue soft reset P0 L LO SWRST P0 H HI SWRST R0 L 0x0007 W P0 R0 SSYNC Clear soft reset P0 L LO SWRST P0 H HI SWRST R0 L 0x00...

Page 134: ...System Reset and Powerup 3 18 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 135: ...ntrols program flow constantly providing the address of the next instruction to be executed by other parts of the processor Program flow in the chip is mostly linear with the pro cessor executing prog...

Page 136: ...dress of the next instruction to execute Figure 4 1 Program Flow Variations ADDRESS N INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRU...

Page 137: ...ent controller handles interrupt and event pro cessing determines whether an interrupt is masked and generates the appropriate event vector address In addition to providing data addresses the data add...

Page 138: ...IPEND EVT8 EVT7 EVT6 EVT5 EVT4 EVT3 EVT2 EVT1 EVT0 PERIPHERALS DYNAMIC POWER MANAGEMENT ADDRESS ARITHMETIC UNIT L1 INSTRUCTION MEMORY PROGRAM COUNTER LOOP COMPARATORS FETCH COUNTER INSTRUCTION DECODE...

Page 139: ...sters all sequencer related registers are directly readable and writable by move instructions for example SYSCFG R0 P0 RETI Manually pushing or popping registers to or from the stack is done using the...

Page 140: ...32 bits wide For debug and test registers see Chapter 21 Debug Table 4 1 Non memory mapped Sequencer Registers Register Name Description SEQSTAT Sequencer Status register See Hardware Errors and Exce...

Page 141: ...Description Instruction Fetch 1 IF1 Issue instruction address to IAB bus start compare tag of instruction cache Instruction Fetch 2 IF2 Wait for instruction data Instruction Fetch 3 IF3 Read from IDB...

Page 142: ...next instruction address based on the status of the align ment buffers The sequencer responds by generating the next fetch address in the next cycle provided there is no change of flow The sequencer...

Page 143: ...the EX1 and EX2 stages L The sequencer ensures that the pipeline is fully interlocked and that all the data hazards are hidden from the programmer Multi cycle instructions behave as multiple single c...

Page 144: ...nstruction s matching return instruction allowing easy return from the subroutine A return instruction causes the sequencer to fetch the instruction at the return address which is stored in the RETS r...

Page 145: ...ge of 4096 to 4094 bytes The PC relative offset for the long jump is a 25 bit immediate value that must also be a multiple of two bit 0 must be a 0 The 25 bit value gives an effective dynamic range of...

Page 146: ...25 bit value gives an effective dynamic range of 16 777 216 to 16 777 214 bytes A direct CALL instruction is always a 4 byte instruction Indirect Branch and Call The indirect JUMP and CALL instructio...

Page 147: ...e CALL instruction the RETS register is loaded with the address of the instruction which would have executed next had the CALL instruction not executed For example JUMP PC P3 CALL PC P0 Subroutines Su...

Page 148: ...it also writes the return address into the RETS register The RETS register holds the address where program execution resumes after the RTS instruction executes In the example this is the location tha...

Page 149: ...iables and Parameter Passing Many subroutines require input arguments from the calling function and need to return their results Often this is accomplished by project wide conventions that certain cor...

Page 150: ...R7 1 R5 R6 R7 calculate anything R6 R6 R7 FP 4 R5 R5 4 FP 8 R6 R6 2 R7 5 SP multiple pop FP SP restore frame pointer RTS _sub end Since the stack pointer SP is modified inside the subroutine for loca...

Page 151: ...ined by the equivalent code sequences The following subroutine does the same job as the one above but it also saves the RETS register to enable nested subroutine calls Therefore the value stored to FP...

Page 152: ...32 bit variables and initializes them to zero when the routine is entered _sub3 LINK 8 SP R7 0 P5 0 R7 0 Z FP 4 R7 FP 8 R7 R7 0 P5 0 SP UNLINK RTS _sub3 end For more information on the LINK and UNLINK...

Page 153: ...for the value of CC The interpretation is to branch on true or branch on false The comparison operations have the form CC expr where expr involves a pair of registers of the same type for example Dat...

Page 154: ...ional Register Move Register moves can be performed depending on whether the value of the CC flag is true or false 1 or 0 In some cases using this instruction instead of a branch eliminates the cycles...

Page 155: ...nt to the Instruction Fetch Address bus at the beginning of the DF1 stage All unconditional branches have a latency of 4 CCLK cycles Consider the example in Table 4 4 Hardware Loops The sequencer supp...

Page 156: ...with two iterations At the beginning the count is 2 Upon reaching the first loop end the count is decremented to 1 and the program flow jumps back to the top of the loop to execute a second time Upon...

Page 157: ...oop are computed as PC relative addresses from the LSETUP instruction plus an offset In each case the offset value is added to the location of the LSETUP instruction The LC0 and LC1 registers are unsi...

Page 158: ..._start Therefore zero start offsets are pre ferred that is the lp_start label is next the LSETUP instruction The processor has no restrictions regarding which instructions can occur in a loop end posi...

Page 159: ...it 1 on a particular instruction PC LB1 LC1 2 will prevent loop unit 0 from looping back on that same instruction even if the address matches Loop unit 0 is allowed to loop back only after the loop co...

Page 160: ...d Similarly the final calculations are done after the loop terminates for example define N 1024 global_setup I0 H 0xFF80 I0 L 0x0000 B0 I0 L0 N 2 Z I1 H 0xFF90 I1 L 0x0000 B1 I1 L1 N 2 Z P5 N 1 Z algo...

Page 161: ...ns a CALL instruction that invokes an unknown subroutine that may have local loops In scenarios like these the loop environment can be saved and restored by pushing and popping the loop registers For...

Page 162: ...pending on the order that the loop registers are popped For best performance restore the LCx regis ters last Furthermore it is recommended that interrupt service routines and global subroutines that c...

Page 163: ...each pop will incur a ten cycle replay penalty Popping or writing LC0 always incurs the penalty LT0 SP LB0 SP LC0 SP This will cause a replay that is a ten cycle refetch Restore other registers here R...

Page 164: ...all system interrupts The SIC provides mapping between the many peripheral interrupt sources and the prioritized general purpose interrupt inputs of the core This mapping is programmable and individua...

Page 165: ...ke up the core from an idled state based on this interrupt request 3 SIC_IMASK masks off or enables interrupts from peripherals at the system level If Interrupt A is not masked the request proceeds to...

Page 166: ...less the inter rupt service routine clears the mechanism that generated Interrupt A or if the process of servicing the interrupt clears this bit It should be noted that emulation reset NMI and excepti...

Page 167: ...your part An interrupt service routine that supports multiple interrupt sources must interrogate the appropriate system memory mapped registers MMRs to determine which peripheral generated the interr...

Page 168: ...t simply by enabling the appropriate bit in the System Interrupt Wakeup enable register SIC_IWR refer to the System Interrupt Appendix of the Blackfin Processor Hardware Reference for your part If a p...

Page 169: ...K the core wakes up if it is idled but it does not generate an interrupt For a listing of the default System Interrupt Wakeup Enable register set tings refer to the System Interrupt Appendix of the Bl...

Page 170: ...ver the rele vant SIC_ISR bit is not cleared unless the service routine clears the mechanism that generated the interrupt Many systems need relatively few interrupt enabled peripherals allowing each p...

Page 171: ...Reference for your part If more than one interrupt source is mapped to the same interrupt they are logically ORed with no hardware prioritization Software can prioritize the interrupt pro cessing as...

Page 172: ...IPEND interrupts pending These three registers are accessible in Supervisor mode only IMASK Register The Core Interrupt Mask register IMASK indicates which interrupt levels are allowed to be taken The...

Page 173: ...de To clear bit N from ILAT first make sure that IMASK N 0 and then write ILAT N 1 This write functionality to ILAT is provided for cases where latched interrupt requests need to be cleared cancelled...

Page 174: ...nding bit in IPEND is set The least significant bit in IPEND that is currently set indicates the interrupt that is currently being serviced At any given time IPEND holds the current status of all nest...

Page 175: ...vectors are not determined by a fixed offset from an interrupt vector table base address This approach minimizes latency by not requiring a long jump from the vector table to the actual ISR code Figur...

Page 176: ...tion EVT0 0xFFE0 2000 Highest priority Vec tor address is provided by JTAG RST Reset EVT1 0xFFE0 2004 NMI NMI EVT2 0xFFE0 2008 EVX Exception EVT3 0xFFE0 200C Reserved Reserved EVT4 0xFFE0 2010 Reserve...

Page 177: ...nterrupt nesting is not enabled If however nesting is enabled and the respective service routine must be interruptible by an interrupt of higher priority the RETI register must be saved most likely on...

Page 178: ...etic status R7 0 P5 0 SP pop core registers RETI SP disable nesting RTI return from interrupt isr end See Nesting of Interrupts on page 4 51 for more details on interrupt nesting Emulation Events NMI...

Page 179: ...hest priority interrupt in IPEND is cleared Emulation Interrupt An emulation event causes the processor to enter Emulation mode where instructions are read from the JTAG interface It is the highest pr...

Page 180: ...ces a system reset for core and peripherals The reset vector is determined by the processor system It points to the start of the on chip boot ROM or to the start of external asynchronous memory depend...

Page 181: ...IVG15 General purpose interrupts are used for any event that requires processor attention For instance a DMA controller may use them to signal the end of a data transmission or a serial communication...

Page 182: ...When multiple instructions need to be atomic or are too time critical to be delayed by an interrupt disable the general purpose interrupts but be sure to re enable them at the conclusion of the code...

Page 183: ...ruction and all instructions after it are aborted 2 The return address is saved in the appropriate return register The return register is RETI for interrupts RETX for exceptions RETN for NMIs and RETE...

Page 184: ...hapter 16 External Event Management Often the RAISE instruction is executed in interrupt service routines to degrade the interrupt priority This enables less urgent parts of the service routine to be...

Page 185: ...interrupt service routine must be saved in the Supervisor stack To return from a non nested interrupt service routine only the RTI instruction must be executed because the return address is already he...

Page 186: ...I0 A3 A4 A5 A6 A7 A3 A4 A5 A6 A3 A4 A5 A4 A3 A3 In In INTERRUPTS DISABLED DURING THIS INTERVAL CYCLE 1 INTERRUPT IS LATCHED ALL POSSIBLE INTERRUPT SOURCES DETERMINED CYCLE 2 INTERRUPT IS PRIORITIZED...

Page 187: ...DETERMINED CYCLE 2 INTERRUPT IS PRIORITIZED CYCLE 3 ALL INSTRUCTIONS ABOVE A2 ARE KILLED A2 IS KILLED IF IT IS AN RTI OR CLI INSTRUCTION ISR STARTING ADDRESS LOOKUP OCCURS CYCLE 4 I0 INSTRUCTION AT ST...

Page 188: ...ded between load of return address and RTI R7 0 P5 0 SP FP SP ASTAT SP RETI SP Execute RTI which jumps to return address re enables inter rupts and switches to User mode if this is the last nested int...

Page 189: ...ertions from the SIC can occur simultaneously before or during interrupt processing for an inter rupt event that is already detected on this interrupt input For a shared interrupt the IPEND interrupt...

Page 190: ...past a CPLB entry or SRAM block while executing the exception handler calculate the maximum space that all interrupt service routines and the exception handler occupy while they are active and then a...

Page 191: ...struction load operation misses the L1 instruction cache and gener ates a high latency line fill operation then when an interrupt occurs it is not held off until the fill has completed Instead the pro...

Page 192: ...ginal external access is completed before initiating the new load or store If the interrupt service routine finishes execution before the load operation has completed then the processor continues to s...

Page 193: ...hardware errors invoke the Hardware Error Interrupt interrupt IVHW in the Event Vector Table EVT and ILAT IMASK and IPEND registers The Hardware Error Figure 4 11 Sequencer Status Register Sequencer S...

Page 194: ...conditions within the core such as Performance Monitor overflow Peripheral errors Bus timeout errors The list of supported hardware conditions with their related HWERRCAUSE codes appears in Table 4 10...

Page 195: ...n violation occurs Exceptions are also given when illegal instructions or illegal combinations of registers are executed Table 4 10 Hardware Conditions Causing Hardware Error Interrupts Hardware Condi...

Page 196: ...example of an error type event is a CPLB miss L Usually the RETX register contains the correct address to return to To skip over an excepting instruction take care in case the next address is not sim...

Page 197: ...x21 E May be used to emulate instructions that are not defined for a particular processor implementation Illegal instruction combination 0x22 E See section for multi issue rules in the ADSP BF53x BF56...

Page 198: ...set Instruction fetch mis aligned address viola tion 0x2A E Attempted misaligned instruction cache fetch On a misaligned instruction fetch exception the return address provided in RETX is the destinat...

Page 199: ...tch address Illegal use of supervi sor resource 0x2E E Attempted to use a Supervisor register or instruction from User mode Supervisor resources are registers and instructions that are reserved for Su...

Page 200: ...excepting instruction is not committed All writebacks from the instruction are prevented The generated exception is not taken 9 Illegal Combination 0x22 10 Illegal Use of Protected Resource 0x2E 11 DA...

Page 201: ...e address of the most recent instruction to cause an exception This mechanism is not intended for recovery but rather for detection Exceptions and the Pipeline Interrupts and exceptions treat instruct...

Page 202: ...r use the Force Interrupt Reset instruction RAISE L When deferring the processing of an exception to lower priority interrupt IVGx the system must guarantee that IVGx is entered before returning to th...

Page 203: ...t for an event is as follows Here processing is deferred to low priority interrupt IVG15 Also parameter passing would typically be done here _EVENT1 RAISE 15 JUMP S _EXIT Entry for event at IVG14 _EVE...

Page 204: ...ll addr_event1 _EVTABLE addr_event2 _EVTABLE 2 addr_eventN _EVTABLE 2N Example Code for an Exception Routine The following code provides an example framework for an interrupt rou tine jumped to from a...

Page 205: ...upport to keep data transport between memory and core registers effi cient and seamless Having a separate arithmetic unit for address calculations prevents the data computation block from being burden...

Page 206: ...ress for the next move Supply address with offset Provides an address from a base with an offset without incrementing the original address pointer Modify address Increments or decrements the stored ad...

Page 207: ...ve For example the R0 I0 M1 instruction directs the DAG to Output the address in register I0 Load the contents of the memory location pointed to by I0 into R0 Modify the contents of I0 by the value co...

Page 208: ...ister used programs must initialize the corresponding L registers to zero for linear addressing or to the buffer length for circular buffer addressing Note all data address registers must be initializ...

Page 209: ...igned to any byte Depending on the type of data used increments and decrements to the address registers can be by 1 2 or 4 to match the 8 16 or 32 bit accesses For example consider the following instr...

Page 210: ...to the last used location on the runtime stack P registers are 32 bits wide Although P registers are primarily used for address calculations they may also be used for general integer arithmetic with...

Page 211: ...plicitly uses the Supervisor Stack Pointer as the effective address To manipulate the User Stack Pointer for code running in Supervi sor mode use the register alias USP When in Supervisor mode a regis...

Page 212: ...an offset value that is added to one of the Index registers or subtracted from it The B and L Length registers define circular buffers The B register con tains the starting address of a buffer and the...

Page 213: ...d stores For example B P1 R0 stores the 8 bit value from the R0 register in the address pointed to by the P1 register then increments the P1 register Loads With Zero or Sign Extension When a 32 bit re...

Page 214: ...the Pointer and Index registers after the access The amount of increment depends on the word size An access of 32 bit words results in an update of the Pointer by 4 A 16 bit word access updates the P...

Page 215: ...tions and can support only a 32 bit word transfer Post modify Addressing Post modify addressing uses the value in the Index or Pointer registers as the effective address and then modifies it by the co...

Page 216: ...of addresses containing data that the DAG steps through repeatedly wrapping around to repeat stepping through the same range of addresses in a circular pattern The DAGs use four types of data address...

Page 217: ...t modifying and updating the index on each access with a positive or negative modify value from the M register If the Index pointer falls outside the buffer range the DAG subtracts the length of the b...

Page 218: ...alue exceeds the buffer length the DAG sub tracts for a positive modify value or adds for a negative modify value the L register value before writing the updated index value to the I register Figure 5...

Page 219: ...t reversed Addresses To obtain results in sequential order programs need bit reversed carry addressing for some algorithms particularly Fast Fourier Transform FFT calculations To satisfy the requireme...

Page 220: ...tes I1 with the new value Memory Address Alignment The processor requires proper memory alignment to be maintained for the data size being accessed Unless exceptions are disabled violations of memory...

Page 221: ...and Transfer Sizes Addressing Mode Types of Transfers Supported Transfer Sizes Auto increment Auto decrement Indirect Indexed To and from Data Registers LOADS 32 bit word 16 bit zero extended half wo...

Page 222: ...asterisk indicates the processor supports the addressing mode Table 5 2 Addressing Modes 32 bit word 16 bit half word 8 bit byte Sign zero extend Data Register Pointer register Data Register Half P Au...

Page 223: ...ster Dreg_hi denotes the upper 16 bits of any Data Register File register Preg denotes any Pointer register FP or SP register Ireg denotes any Index register Mreg denotes any Modify register W denotes...

Page 224: ...struction Summary Instruction Preg Preg Preg Preg Preg Preg Preg Preg uimm6m4 Preg Preg uimm17m4 Preg Preg uimm17m4 Preg FP uimm7m4 Dreg Preg Dreg Preg Dreg Preg Dreg Preg uimm6m4 Dreg Preg uimm17m4 D...

Page 225: ...X Dreg W Preg X Dreg W Preg uimm5m2 X Dreg W Preg uimm16m2 X Dreg W Preg uimm16m2 X Dreg W Preg Preg X Dreg_hi W Ireg Dreg_hi W Ireg Dreg_hi W Ireg Dreg_hi W Preg Dreg_hi W Preg Preg Dreg_lo W Ireg Dr...

Page 226: ...X Dreg B Preg uimm15 X Dreg B Preg uimm15 X Preg Preg Preg Preg Preg Preg Preg uimm6m4 Preg Preg uimm17m4 Preg Preg uimm17m4 Preg FP uimm7m4 Preg Preg Dreg Preg Dreg Preg Dreg Preg uimm6m4 Dreg Preg...

Page 227: ...eg_hi W Preg Preg Dreg_hi W Ireg Dreg_lo W Ireg Dreg_lo W Ireg Dreg_lo W Preg Dreg_lo W Preg Dreg W Preg Dreg W Preg Dreg W Preg uimm5m2 Dreg W Preg uimm16m2 Dreg W Preg uimm16m2 Dreg W Preg Preg Dreg...

Page 228: ...t of multi issue opera tions Data can be loaded and stored in parallel to arithmetical operations For details see Chapter 20 Issuing Parallel Instructions Preg Preg BREV Ireg Mreg BREV Preg Preg 2 Pre...

Page 229: ...can be configured to function as cache memory Some Blackfin derivatives also feature on chip Level 2 L2 memories Based on a Von Neumann architecture L2 memories have a unified purpose and can freely...

Page 230: ...ckfin processors Overview of On Chip Level 1 L1 Memory The L1 memory system performance provides high bandwidth and low latency Because SRAMs provide deterministic access time and very high throughput...

Page 231: ...core accesses SRAM access at processor clock rate CCLK for critical DSP algo rithms and fast context switching Figure 6 1 Processor Memory Architecture NON DMA PERIPHERALS EBIU DMA CONTROLLER L1 MEMOR...

Page 232: ...uld be mapped to the scratchpad memory for the fastest context switching during interrupt handling L The scratchpad data SRAM like the other L1 blocks operates at core clock frequency CCLK It can be a...

Page 233: ...ability Protection Lookaside Buffer CPLB address checking is dis abled see L1 Instruction Cache on page 6 10 When the LRUPRIORST bit is set to 1 the cached states of all CPLB_LRUPRIO bits see ICPLB_DA...

Page 234: ...ers must specify desired memory pages as cache enabled Instruction CPLBs are disabled by default after reset When disabled only minimal address checking is performed by the L1 memory interface This mi...

Page 235: ...6 2 L1 Instruction Memory Control Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 L1 Instruction Memory Control Regist...

Page 236: ...ch 16K byte bank is made up of four 4K byte subbanks In the figure dotted lines indicate features that exist only on some Blackfin processors Please refer to the hardware reference manual for your par...

Page 237: ...B 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB DMA CORE BUS DCB INSTRUCTION DATA BUS IDB REGISTER ACCESS BUS RAB TO PROCESSOR CORE INSTRUCTION BANK A INSTRUCTION BANK B INSTRUCTION BANK C UP TO 32 KB...

Page 238: ...Bs will be cached When CPLBs are enabled any memory location that is accessed must have an associated page definition available or a CPLB exception is generated CPLBs are described in Memory Pro tecti...

Page 239: ...rithm used to determine which cache line should be replaced if a cache miss occurs The Valid bit indicates the state of a cache line A cache line is always valid or invalid Invalid cache lines have th...

Page 240: ...1 WD0 LINE 3 VALID LRU ADDRESS WD3 WD2 WD1 WD0 LINE 2 VALID LRU ADDRESS WD3 WD2 WD1 WD0 LINE 1 VALID LRU ADDRESS WD3 WD2 WD1 WD0 LINE 0 1 2 1 20 4 x 64 WAY 2 VALID LRU ADDRESS WD3 WD2 WD1 WD0 LINE 31...

Page 241: ...the four ways and the respective cache line is valid a cache hit occurs If the address tag compare operation does not result in a match in any of the four ways or the respective line is not valid a ca...

Page 242: ...et instruction word When responding to a line read request from the instruction mem ory unit the external memory returns the target instruction word first After it has returned the target instruction...

Page 243: ...mory unit is configured as cache bits 9 through 5 of the instruction fetch address are used as the index to select the cache set for the tag address compare operation If the tag address compare operat...

Page 244: ...struction tag and data arrays indi rectly and provide a mechanism for instruction cache test initialization and debug L The coherency of instruction cache must be explicitly managed To accomplish this...

Page 245: ...ion Cache Locking by Way The instruction cache has four independent lock bits ILOC 3 0 that control each of the four Ways of the instruction cache When the cache is enabled L1 Instruction Memory has f...

Page 246: ...of the instruction is gen erated from the P registers Because the instruction cache should not contain modified dirty data the cache line is simply invalidated and not flushed In the following example...

Page 247: ...dating the cache and a CSYNC instruction should be inserted after each of these operations Instruction Test Registers The Instruction Test registers allow arbitrary read write of all L1 cache entries...

Page 248: ...struction Test Data 1 Register on page 6 22 Figure 6 8 Instruction Test Data 0 Register on page 6 23 Access to these registers is possible only in Supervisor or Emulation mode When writing to ITEST re...

Page 249: ...27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 Instruction Test Command Register ITEST_COMMAND 00 Access subbank 0 01 Access subbank 1 10 Access subbank 2 11 Access subbank 3 Address bits 13 12 in SRAM SB...

Page 250: ...8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X...

Page 251: ...3 2 Tag 1 0 X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Data 31 16 Data 15 0 Used to access L...

Page 252: ...it data loads One pipelined 32 bit data store One DMA I O up to 64 bits One 64 bit cache fill victim access L L1 Data Memory can be used only to store data DMEM_CONTROL Register The Data Memory Contro...

Page 253: ...AG1 non cacheable fetches use port B PORT_PREF0 DAG0 Port Preference 0 DAG0 non cacheable fetches use port A 1 DAG0 non cacheable fetches use port B Valid only when DMC 1 0 11 Determines whether Addre...

Page 254: ...o affect unless both Data Bank A and Data Bank B are serving as cache bits DMC 1 0 in this register are set to 11 The ENDCPLB bit is used to enable disable the 16 Cacheability Protection Lookaside Buf...

Page 255: ...tch the same 16K byte half bank address bits 16 match and the same bank address bits 21 and 20 match When an address collision is detected access is nominally granted first to the DAGs then to the sto...

Page 256: ...4 KB STORE BUFFER 6 X 32 BIT TO PROCESSOR CORE TO DMA CONTROLLER TO EBIU AND L2 DMA DCB DMA READ READ WRITE WRITE EAB 32 BIT 32 BIT 32 BIT 64 BIT 32 BIT 32 BIT 32 BIT 64 BIT LD1 32 BIT LD0 32 BIT SD 3...

Page 257: ...o affect which addresses tend to remain resident in cache by avoiding victimization of repetitively used sets Accesses to cache do not collide unless they are to the same 4K byte sub bank the same hal...

Page 258: ...e of how the cacheable address space maps into two data banks follows When both banks are configured as cache they operate as two indepen dent 16K byte 2 Way set associative caches that can be indepen...

Page 259: ...16K byte pages of memory map into each of the two 16K byte caches implemented by the two data banks Consequently Any data in the first 16K byte of memory could be stored only in Data Bank B Any data...

Page 260: ...ory it is effectively served by only half the cache that is by Data Bank B a 2 Way set associative 16K byte cache In this instance the application never derives any benefit from Data Bank A L For most...

Page 261: ...s against the tag bits If the logical address is present in L1 cache a cache hit occurs and the data is accessed in L1 If the logical address is not present a cache miss occurs and the memory transact...

Page 262: ...fill request to the system as critical or requested word first and forwards that data to the waiting DAG as it updates the cache line In other words the cache performs critical word forwarding The da...

Page 263: ...bank In addition a two entry write buffer in the L1 Data Memory accepts all stores with cache inhibited or store through protec tion An SSYNC instruction flushes the write buffer IPRIO Register and Wr...

Page 264: ...ter 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 Interrupt Priority Register IPRIO Reset 0x0000...

Page 265: ...ied cache line with external memory If the cached data line is dirty the instruction writes the line out and marks the line clean in the data cache If the specified data cache line is already clean or...

Page 266: ...gister to set the DMC 1 0 bits to their previous state then configures the data memory back to its previous cache SRAM configuration An SSYNC instruction should be run before invalidating the cache an...

Page 267: ...egisters is possible only in Supervisor or Emulation mode When writing to DTEST registers always write to the DTEST_DATA registers first then the DTEST_COMMAND register DTEST_COMMAND Register When the...

Page 268: ...11 0 Access Way0 Instruction bit 11 0 1 Access Way1 Instruction bit 11 1 Data Instruction Access 0 Access Data 1 Access Instruction 0 Read access 1 Write access Array Access 0 Access tag array 1 Acce...

Page 269: ...s Figure 6 14 Data Test Data 1 Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X...

Page 270: ...16 X X X X X X X X 15 14 13 12 11 1 0 X X X Data Test Data 0 Register DTEST_DATA0 Reset Undefined Valid 0 Cache line invalid 1 Cache line valid X Tag 19 4 Tag 3 2 Tag Dirty 0 Cache line unmodified sin...

Page 271: ...ry itself They also provide proper bus and DMA infrastructure Wide buses between L1 and L2 memory guarantee high data throughput A dedicated DMA controller called IMDMA supports data exchange between...

Page 272: ...mple at the end of 15 core cycles 32 bytes of instructions or data have been brought into cache and are available to the sequencer If all the instructions contain 16 bits sixteen instructions are brou...

Page 273: ...ill takes seven core cycles to complete As shown in Figure 6 17 on page 6 46 on chip L2 memory is configured as non cacheable To illustrate the con cept of L2 latency with cache off simple instruction...

Page 274: ...les added to the execution of the instruction Because the L1 memories are separated into instruction and data memo ries the CPLB entries are also divided between instruction and data CPLBs Sixteen CPL...

Page 275: ...B_DATA n defines the properties of the page described by the CPLB descriptor For data operations DCPLB_ADDR m defines the start address of the page described by the CPLB descriptor DCPLB_DATA m define...

Page 276: ...and I O Memory Page Attributes Each page is defined by a two word descriptor consisting of an address descriptor word xCPLB_ADDR n and a properties descriptor word xCPLB_DATA n The address descriptor...

Page 277: ...as last loaded This must be managed by software and does not change status automatically Supervisor write access permission Enables or disables writes to this page when in Supervisor mode Data pages o...

Page 278: ...cover the addressable memory and I O spaces than will fit into the available on chip CPLB MMRs When this happens a memory based data structure called a Page Descriptor Table is used in it can be store...

Page 279: ...ects one of the descriptors to be replaced and the new descriptor information is loaded Before loading new descrip tor data into any CPLBs the corresponding group of sixteen CPLBs must be disabled usi...

Page 280: ...not support automatic address translation in hardware If all L1 memory is configured as SRAM then the data and instruction MMU functions are optional depending on the application s need for protection...

Page 281: ...r the L1 Data Memory is configured partially or entirely as cache the corresponding CPLBs must be enabled When an instruction generates a memory request and the cache is enabled the processor first ch...

Page 282: ...e some ICPLBs and DCPLBs have com mon descriptors for the same address space Figure 6 18 Examples of Protected Memory Regions INSTRUCTION CPLB SETUP DATA CPLB SETUP ASYNC CACHEABLE TWO 1MB PAGES L1 IN...

Page 283: ...11 4M byte page size PAGE_SIZE 1 0 Reset 0x0000 0000 CPLB_LOCK CPLB_VALID CPLB_L1_CHBL Clear this bit whenever L1 memory is configured as SRAM 0 Non cacheable in L1 1 Cacheable in L1 0 Invalid disable...

Page 284: ...PLB_DATA0 0xFFE0 1200 ICPLB_DATA1 0xFFE0 1204 ICPLB_DATA2 0xFFE0 1208 ICPLB_DATA3 0xFFE0 120C ICPLB_DATA4 0xFFE0 1210 ICPLB_DATA5 0xFFE0 1214 ICPLB_DATA6 0xFFE0 1218 ICPLB_DATA7 0xFFE0 121C ICPLB_DATA...

Page 285: ...through cacheable CPLB_VALID 1 CPLB_WT 1 0 Allocate cache lines on reads only 1 Allocate cache lines on reads and writes Valid only if write back cacheable CPLB_VALID 1 CPLB_WT 0 and CPLB_L1_CHBL 1 0...

Page 286: ...PLB_DATA0 0xFFE0 0200 DCPLB_DATA1 0xFFE0 0204 DCPLB_DATA2 0xFFE0 0208 DCPLB_DATA3 0xFFE0 020C DCPLB_DATA4 0xFFE0 0210 DCPLB_DATA5 0xFFE0 0214 DCPLB_DATA6 0xFFE0 0218 DCPLB_DATA7 0xFFE0 021C DCPLB_DATA...

Page 287: ...E0 0104 DCPLB_ADDR2 0xFFE0 0108 DCPLB_ADDR3 0xFFE0 010C DCPLB_ADDR4 0xFFE0 0110 DCPLB_ADDR5 0xFFE0 0114 DCPLB_ADDR6 0xFFE0 0118 DCPLB_ADDR7 0xFFE0 011C DCPLB_ADDR8 0xFFE0 0120 DCPLB_ADDR9 0xFFE0 0124...

Page 288: ...xFFE0 0138 DCPLB_ADDR15 0xFFE0 013C Figure 6 22 ICPLB Address Registers Table 6 4 DCPLB Address Register Memory mapped Addresses Cont d Register Name Memory mapped Address 0 0 0 0 0 0 0 0 0 0 15 14 13...

Page 289: ...S and ICPLB_STATUS registers are valid only while in the faulting exception service routine Table 6 5 ICPLB Address Register Memory mapped Addresses Register Name Memory mapped Address ICPLB_ADDR0 0xF...

Page 290: ...d exception see Figure 6 24 Figure 6 23 DCPLB Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X 0 X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0...

Page 291: ...DDR and ICPLB_FAULT_ADDR registers are valid only while in the faulting exception service routine Figure 6 24 ICPLB Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X 0 X X X X X X X...

Page 292: ...defined FAULT_ADDR 15 0 Data address that has caused a fault in the L1 Data Memory FAULT_ADDR 31 16 Data address that has caused a fault in L1 Data Memory 0xFFE0 000C 31 30 29 28 27 26 25 24 23 22 21...

Page 293: ...nd the least significant byte in the low address byte B0 in addr The diagram on the right shows 32 bit instructions stored in memory Note the most significant 16 bit half word of the instruction bytes...

Page 294: ...on per clock cycle and it implies that the synchronization between when writes complete and when subsequent instructions execute is not guaranteed Moreover this syn chronization is considered unimport...

Page 295: ...the sequence of the pro gram source code All that is guaranteed is Load operations will complete before the returned data is used by a subsequent instruction Load operations using data previously writ...

Page 296: ...these effects could cause undesirable side effects in the intended operation of the program and peripheral To ensure that these effects do not occur in code that requires precise strong ordering of lo...

Page 297: ...mories and the rest of the chip In addition to performing the core synchronization functions of CSYNC the SSYNC instruction flushes any write buffers between the L1 memory and the system domain and ge...

Page 298: ...r the instruction should have executed On chip peripherals are guarded against destruction due to speculative reads There a separate strobe triggers the read side effect when the instruction actually...

Page 299: ...n tasks It also con tains a brief discussion of MMR registers and a core MMR programming example Alignment Nonaligned memory operations are not directly supported A nonaligned memory reference generat...

Page 300: ...ted by the core If this happens the TESTSET instruction is exe cuted again upon return from the interrupt The TESTSET instruction can address the entire 4G byte memory space but should not target on c...

Page 301: ...after store instructions to guarantee strong ordering of MMR accesses All MMRs are accessible only in Supervisor mode Access to MMRs in User mode generates a protection violation exception All core M...

Page 302: ...stores the contents of the IMASK register thus enabling interrupts The instructions between CLI and STI are not interruptible Terminology The following terminology is used to describe memory cache blo...

Page 303: ...ex invalid Describes the state of a cache line When a cache line is invalid a cache line match cannot occur least recently used LRU algorithm Replacement algorithm used by cache that first replaces li...

Page 304: ...written to memory before it can be replaced to free space for a cache line allocation Way An array of line storage elements in an N Way cache see Figure 6 4 on page 6 12 write back A cache write polic...

Page 305: ...n page 7 8 RTS RTI RTX RTN RTE Return on page 7 10 LSETUP LOOP on page 7 13 Instruction Overview This chapter discusses the instructions that control program flow Users can take advantage of these ins...

Page 306: ...label user defined absolute address label resolved by the assembler linker to the appropriate PC relative instruction a or b Syntax Terminology Preg P5 0 SP FP pcrelm2 undetermined 25 bit or smaller s...

Page 307: ...ifies 16 bit instruction length Comment b identifies 32 bit instruction length Functional Description The Jump instruction forces a new value into the Program Counter PC to change program flow In the...

Page 308: ...rget jump pc p2 P2 relative absolute address of the target and then a presentation of the absolute values for target jump 0x224 offset is positive in 13 bits so target address is PC 0x224 a forward ju...

Page 309: ...the assembler linker to the appropriate PC relative instruction a IF CC JUMP user_label bp user defined absolute address label resolved by the assembler linker to the appropriate PC relative instruct...

Page 310: ...ion length Functional Description The Conditional JUMP instruction forces a new value into the Program Counter PC to change the program flow based on the value of the CC bit The range of valid offset...

Page 311: ...rget address is a backwards branch branch predicted if cc jump 0x0B4 offset is positive so target offset address is a forwards branch branch not predicted if cc jump 0xFFFFFC22 bp negative offset in 1...

Page 312: ...embler linker to the appropriate PC relative instruction a or b Syntax Terminology Preg P5 0 SP and FP are not allowed as the source register for this instruction pcrel25m2 25 bit signed even PC relat...

Page 313: ...LL instruction exe cutes the RETS register contains the address of the next instruction The value in the Preg must be an even value to maintain 16 bit alignment Flags Affected None Required Mode User...

Page 314: ...TE Return from Emulation a Instruction Length In the syntax comment a identifies 16 bit instruction length Functional Description The Return instruction forces a return from a subroutine maskable or N...

Page 315: ...gnized but not serviced until the current interrupt service routine concludes Restoring RETI back off the stack at the conclusion of the interrupt service routine masks subsequent interrupts until the...

Page 316: ...Instruction Overview 7 12 ADSP BF53x BF56x Blackfin Processor Programming Reference Example rts rti rtx rtn rte Also See Call SP Push SP Pop Special Applications None...

Page 317: ...OOP loop_name LC0 Preg autoinitialize LC0 b LOOP loop_name LC0 Preg 1 autoinit LC0 b LOOP_BEGIN loop_name define the 1st instruction of loop b LOOP_END loop_name define the last instruction of the loo...

Page 318: ...lates the three instructions together LSETUP pcrel5m2 lppcrel11m2 LC1 b LSETUP pcrel5m2 lppcrel11m2 LC1 Preg autoinitial ize LC1 b LSETUP pcrel5m2 lppcrel11m2 LC1 Preg 1 autoini tialize LC1 b Syntax T...

Page 319: ...egisters each to support two independent nestable loops The registers are Loop_Top LTn Loop_Bottom LBn and Loop_Count LCn Consequently LT0 LB0 and LC0 describe Loop0 and LT1 LB1 and LC1 describe Loop1...

Page 320: ...the loop pointers to be executed as straight line code In the instruction syntax the designation of the loop counter LC0 or LC1 determines which loop level is initialized Consequently to initialize Lo...

Page 321: ...the LSETUP instruction Begin_Loop and End_Loop are typi cally address labels The linker replaces the labels with offset values A loop counter register LC0 or LC1 counts the trips through the loop The...

Page 322: ...defined loop execute normally Also the last instruction in the loop must not modify the registers that define the currently active loop LCn LTn or LBn User modifications to those registers while the h...

Page 323: ...n DoItSome place before the first instruction in the loop loop_end DoItSome place after the last instruction in the loop loop MyLoop LC1 define loop MyLoop with Loop Counter 1 loop_begin MyLoop place...

Page 324: ...Instruction Overview 7 20 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 325: ...Zero Extended on page 8 15 Load Half Word Sign Extended on page 8 19 Load High Data Register Half on page 8 23 Load Low Data Register Half on page 8 27 Load Byte Zero Extended on page 8 31 Load Byte S...

Page 326: ...amming Reference Instruction Overview This chapter discusses the load store instructions Users can take advan tage of these instructions to load and store immediate values pointer registers data regis...

Page 327: ...to high half data or address register b Zero Extended reg uimm16 Z 16 bit value zero extended into data or address register b A0 0 Clear A0 register b A1 0 Clear A1 register b A1 A0 0 Clear both A1 an...

Page 328: ...Length In the syntax comment a identifies 16 bit instruction length Comment b identifies 32 bit instruction length Functional Description The Load Immediate instruction loads immediate values or expl...

Page 329: ...the correct half word portion of the 32 bit literal for inclusion in the instruction word The zero extended versions fill the upper bits of the destination register with zeros The sign extended versi...

Page 330: ...ction Overview 8 6 ADSP BF53x BF56x Blackfin Processor Programming Reference a0 0 a1 0 a1 a0 0 Also See Load Pointer Register Special Applications Use the Load Immediate instruction to initialize regi...

Page 331: ...indexed with large offset b Preg FP uimm7m4 indexed FP relative a Syntax Terminology Preg P5 0 SP FP uimm6m4 6 bit unsigned field that must be a multiple of 4 with a range of 0 through 60 bytes uimm7...

Page 332: ...onstant Offset the source pointer with a large 18 bit word aligned mul tiple of 4 signed constant Frame Pointer FP relative and offset with a 7 bit word aligned multiple of 4 negative constant The ind...

Page 333: ...s instruction can be issued in parallel with spe cific other instructions For more information see Issuing Parallel Instructions on page 20 1 The 32 bit versions of this instruction cannot be issued i...

Page 334: ...ith small offset a Dreg Preg uimm17m4 indexed with large offset b Dreg Preg uimm17m4 indexed with large offset b Dreg Preg Preg indirect post increment index a 1 Dreg FP uimm7m4 indexed FP relative a...

Page 335: ...ess and offset must yield an even multiple of 4 to main tain 4 byte word address alignment Failure to maintain proper alignment causes a misaligned memory access exception L The instruction versions t...

Page 336: ...me Pointer FP relative and offset with a 7 bit word aligned multiple of 4 negative constant The indexed FP relative form is typically used to access local variables in a subroutine or function Positiv...

Page 337: ...ndirect post increment index version must have separate P registers for the input operands If a common Preg is used for the inputs the auto increment feature does not work Flags Affected None Required...

Page 338: ...r1 p0 p1 r5 fp 12 r2 i2 r0 i0 r0 i0 Before indirect post increment indexed addressing r7 0 i3 0x4000 Memory location contains 15 for example m0 4 r7 i3 m0 Afterwards r7 15 from memory location 0x4000...

Page 339: ...small offset a Dreg W Preg uimm16m2 Z indexed with large offset b Dreg W Preg uimm16m2 Z indexed with large offset b Dreg W Preg Preg Z indirect post increment index a 1 Syntax Terminology Dreg R7 0...

Page 340: ...r half of the register The Pointer register is a P register The indirect address and offset must yield an even numbered address to maintain 2 byte half word address alignment Failure to maintain prope...

Page 341: ..._2 where Dest is the destination register Dreg in the syntax example Src_1 is the first source register on the right hand side of the equation Src_2 is the second source register Indirect and post inc...

Page 342: ...her instructions Example r3 w p0 z r7 w p1 z r2 w sp z r6 w p2 12 z r0 w p4 0x8004 z r1 w p0 p1 z Also See Load Half Word Sign Extended Load Low Data Register Half Load High Data Register Half Load Da...

Page 343: ...small offset a Dreg W Preg uimm16m2 X indexed with large offset b Dreg W Preg uimm16m2 X indexed with large offset b Dreg W Preg Preg X indirect post increment index a 1 Syntax Terminology Dreg R7 0...

Page 344: ...aded is repli cated in the whole upper half word of the destination D register The indirect address and offset must yield an even numbered address to maintain 2 byte half word address alignment Failur...

Page 345: ...rc_2 where Dest is the destination register Dreg in the syntax example Src_1 is the first source register on the right hand side of the equation Src_2 is the second source register L Indirect and post...

Page 346: ...el with other instructions Example r3 w p0 x r7 w p1 x r2 w sp x r6 w p2 12 x r0 w p4 0x800E x r1 w p0 p1 x Also See Load Half Word Zero Extended Load Low Data Register Half Load High Data Register Ha...

Page 347: ...ect a Dreg_hi W Preg Preg indirect post increment index a 1 Syntax Terminology Dreg_hi R7 0 H Preg P5 0 SP FP Ireg I3 0 Instruction Length In the syntax comment a identifies 16 bit instruction length...

Page 348: ...he Ireg used in this instruction Example If you use I2 to increment your address pointer first clear L2 to disable circular buffering Failure to explicitly clear Lreg beforehand can result in unexpect...

Page 349: ...i is the most significant half of the destination register Dreg_hi in the syntax example Src_1 is the memory source pointer register on the right hand side of the syntax Src_2 is the increment pointer...

Page 350: ...w i3 r1 h w i0 r2 h w p4 r5 h w p2 p0 Also See Load Low Data Register Half Load Half Word Zero Extended Load Half Word Sign Extended Special Applications To read consecutive aligned 16 bit values for...

Page 351: ...lo W Preg Preg indirect post increment index a 1 Syntax Terminology Dreg_lo R7 0 L Preg P5 0 SP FP Ireg I3 0 Instruction Length In the syntax comment a identifies 16 bit instruction length Functional...

Page 352: ...Register Lreg corresponding to the Ireg used in this instruction Example If you use I2 to increment your address pointer first clear L2 to disable circular buffering Failure to explicitly clear Lreg...

Page 353: ...c_2 where Dst_lo is the least significant half of the destination register Dreg_lo in the syntax example Src_1 is the memory source pointer register on the right side of the syntax Src_2 is the increm...

Page 354: ...ns on page 20 1 Example r3 l w i1 r7 l w i3 r1 l w i0 r2 l w p4 r5 l w p2 p0 Also See Load High Data Register Half Load Half Word Zero Extended Load Half Word Sign Extended Special Applications To rea...

Page 355: ...R7 0 Preg P5 0 SP FP uimm15 15 bit unsigned field with a range of 0 through 32 767 bytes 0x0000 through 0x7FFF Instruction Length In the syntax comment a identifies 16 bit instruction length Comment...

Page 356: ...ement the source pointer by 1 byte Offset the source pointer with a 16 bit signed constant Flags Affected None Required Mode User Supervisor Parallel Issue The 16 bit versions of this instruction can...

Page 357: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 8 33 Load Store Example r3 b p0 z r7 b p1 z r2 b sp z r0 b p4 0xFFFF800F z Also See Load Byte Sign Extended Special Applications None...

Page 358: ...mm15 15 bit unsigned field with a range of 0 through 32 767 bytes 0x0000 through 0x7FFF Instruction Length In the syntax comment a identifies 16 bit instruction length Comment b identifies 32 bit inst...

Page 359: ...the source pointer by 1 byte Offset the source pointer with a 16 bit signed constant Flags Affected None Required Mode User Supervisor Parallel Issue The 16 bit versions of this instruction can be is...

Page 360: ...nstruction Overview 8 36 ADSP BF53x BF56x Blackfin Processor Programming Reference Example r3 b p0 x r7 b p1 x r2 b sp x r0 b p4 0xFFFF800F x Also See Load Byte Zero Extended Special Applications None...

Page 361: ...g indexed with large offset b FP uimm7m4 Preg indexed FP relative a Syntax Terminology Preg P5 0 SP FP uimm6m4 6 bit unsigned field that must be a multiple of 4 with a range of 0 through 60 bytes uimm...

Page 362: ...g options Post increment the destination pointer by 4 bytes Post decrement the destination pointer by 4 bytes Offset the source pointer with a small 6 bit word aligned multi ple of 4 unsigned constant...

Page 363: ...nstruction can be issued in parallel with spe cific other instructions For more information see Issuing Parallel Instructions on page 20 1 The 32 bit versions of this instruction cannot be issued in p...

Page 364: ...small offset a Preg uimm17m4 Dreg indexed with large offset b Preg uimm17m4 Dreg indexed with large offset b Preg Preg Dreg indirect post increment index a 1 FP uimm7m4 Dreg indexed FP relative a Usi...

Page 365: ...ional Description The Store Data Register instruction stores the contents of a 32 bit D reg ister to a 32 bit memory location The destination Pointer register can be a P register I register or the Fra...

Page 366: ...Data Register instruction supports the following options Post increment the destination pointer by 4 bytes Post decrement the destination pointer by 4 bytes Offset the source pointer with a small 6 bi...

Page 367: ..._1 by a quantity indexed by Dst_2 where Src is the source register Dreg in the syntax example Dst_1 is the memory destination register on the left side of the equation Dst_2 is the increment index reg...

Page 368: ...d in parallel with spe cific other instructions For more information see Issuing Parallel Instructions on page 20 1 The 32 bit versions of this instruction cannot be issued in parallel with other inst...

Page 369: ...a W Preg Dreg_hi indirect a W Preg Preg Dreg_hi indirect post increment index a 1 Syntax Terminology Dreg_hi P7 0 H Preg P5 0 SP FP Ireg I3 0 Instruction Length In the syntax comment a identifies 16 b...

Page 370: ...ength Register Lreg corresponding to the Ireg used in this instruction Example If you use I2 to increment your address pointer first clear L2 to disable circular buffering Failure to explicitly clear...

Page 371: ...quantity indexed by Dst_2 where Src_hi is the most significant half of the source register Dreg_hi in the syntax example Dst_1 is the memory destination pointer register on the left side of the synta...

Page 372: ...20 1 Example w i1 r3 h w i3 r7 h w i0 r1 h w p4 r2 h w p2 p0 r5 h Also See Store Low Data Register Half Special Applications To write consecutive aligned 16 bit values for high performance DSP operati...

Page 373: ...o indirect post decrement data addressing a W Preg Dreg_lo indirect a W Preg Dreg indirect a W Preg Dreg indirect post increment a W Preg Dreg indirect post decrement a W Preg uimm5m2 Dreg indexed wit...

Page 374: ...number to maintain 2 byte half word address alignment Failure to maintain proper alignment causes an misaligned memory access exception L The instruction versions that explicitly modify Ireg support o...

Page 375: ...arge 17 bit half word aligned even signed constant Indirect and Post Increment Index Addressing The syntax of the form Dst_1 Dst_2 Src is indirect post increment index addressing The form is shorthand...

Page 376: ...d for the inputs the auto increment feature does not work Flags Affected None Required Mode User Supervisor Parallel Issue The 16 bit versions of this instruction can be issued in parallel with spe ci...

Page 377: ...Special Applications To write consecutive aligned 16 bit values for high performance DSP operations use the Store Data Register instructions instead of these Half Word instructions The Half Word Store...

Page 378: ...t b Syntax Terminology Dreg R7 0 Preg P5 0 SP FP uimm15 15 bit unsigned field with a range of 0 through 32 767 bytes 0x0000 through 0x7FFF Instruction Length In the syntax comment a identifies 16 bit...

Page 379: ...intain byte alignment Offset the destination pointer with a 16 bit signed constant Flags Affected None Required Mode User Supervisor Parallel Issue The 16 bit versions of this instruction can be issue...

Page 380: ...lications To write consecutive 8 bit values for high performance DSP operations use the Store Data Register instructions instead of these byte instructions The byte store instructions use only one fou...

Page 381: ...9 10 Move Half to Full Word Sign Extended on page 9 13 Move Register Half on page 9 15 Move Byte Zero Extended on page 9 23 Move Byte Sign Extended on page 9 25 Instruction Overview This chapter discu...

Page 382: ...g a sysreg Preg 32 bit P register to sysreg a sysreg USP a A0 A1 move 40 bit Accumulator value b A1 A0 move 40 bit Accumulator value b A0 Dreg 32 bit D register to 40 bit A0 sign extended b A1 Dreg 32...

Page 383: ...g_even and Dreg_odd operands must be members of the same register pair for example from the set R1 0 R3 2 R5 4 R7 6 opt_mode Optionally FU S2RND or ISS2 See Table 9 1 on page 9 4 Instruction Length In...

Page 384: ...1 2 31 Signed integer Copy Accumulator 40 0 format to register 32 0 format Saturate results between minimum 231 and maximum 231 1 In either case the resulting hexadecimal range is minimum 0x8000 0000...

Page 385: ...ger with scaling Shift the Accumulator contents one place to the left multiply x 2 Saturate result to 32 0 format Copy to destination register Results range between minimum 1 and maximum 231 1 In eith...

Page 386: ...equent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor for most cases Explicit accesses to USP SEQSTAT SYSCFG RETI...

Page 387: ...with scaling truncation and saturation Also See Load Immediate to initialize registers Move Register Half to move values explicitly into the A0 X and A1 X registers LSETUP LOOP to implicitly access re...

Page 388: ...g R7 0 P5 0 SP FP Instruction Length In the syntax comment a identifies 16 bit instruction length Functional Description The Move Conditional instruction moves source register contents into a destinat...

Page 389: ...Conditional instruction cannot be issued in parallel with other instructions Example if cc r3 r0 move if CC 1 if cc r2 p4 if cc p0 r7 if cc p2 p5 if cc r3 r0 move if CC 0 if cc r2 p4 if cc p0 r7 if cc...

Page 390: ...Functional Description The Move Half to Full Word Zero Extended instruction converts an unsigned half word 16 bits to an unsigned word 32 bits The instruction copies the least significant 16 bits from...

Page 391: ...V is cleared All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADS...

Page 392: ...Instruction Overview 9 12 ADSP BF53x BF56x Blackfin Processor Programming Reference Also See Move Half to Full Word Sign Extended Move Register Half Special Applications None...

Page 393: ...ord Sign Extended instruction converts a signed half word 16 bits to a signed word 32 bits The instruction cop ies the least significant 16 bits from a source register into the lower half of a 32 bit...

Page 394: ...me flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This in...

Page 395: ...cant 16 bits of Dreg b A0 L Dreg_lo least significant 16 bits of Dreg into least significant 16 bits of A0 W b A1 L Dreg_lo least significant 16 bits of Dreg into least significant 16 bits of A1 W b A...

Page 396: ...b Dreg_hi A1 Dreg_lo AO opt_mode move both values at once must go to the upper and lower halves of the same Dreg b Syntax Terminology Dreg_lo R7 0 L Dreg_hi R7 0 H A0 L the least significant 16 bits o...

Page 397: ...ounding beyond a simple Move Register Half instruction The fraction version of this instruction the default option transfers the Accumulator result to the destination register according to the diagram...

Page 398: ...the RND_MOD bit in the ASTAT register when they copy the results into the destination register RND_MOD determines whether biased or unbiased rounding is used RND_MOD controls rounding for all version...

Page 399: ...imum 0 and maximum 1 2 16 or expressed in hex between mini mum 0x0000 and maximum 0xFFFF The Accumulator is unaffected by extraction IS Signed integer format Extract the lower 16 bits of the Accumulat...

Page 400: ...n and copy it to the destination register half Result is between minimum 1 and maximum 1 2 15 or expressed in hex between mini mum 0x8000 and maximum 0x7FFF The Accumulator is unaffected by extraction...

Page 401: ...erate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction c...

Page 402: ...lower halves of the same Dreg r0 h a1 is copy A1 L into R0 H with saturation r5 l a0 t copy A0 H into R5 L truncate A0 L no satu ration r1 l a0 s2rnd copy A0 H into R1 L with scaling round ing satura...

Page 403: ...al Description The Move Byte Zero Extended instruction converts an unsigned byte to an unsigned word 32 bits The instruction copies the least significant 8 bits from a source register into the least s...

Page 404: ...ly than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction cannot be issued...

Page 405: ...ion The Move Byte Sign Extended instruction converts a signed byte to a signed word 32 bits It copies the least significant 8 bits from a source register into the least significant 8 bits of a 32 bit...

Page 406: ...TAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parall...

Page 407: ...on page 10 8 SP Pop Multiple on page 10 12 LINK UNLINK on page 10 17 Instruction Overview This chapter discusses the instructions that control the stack Users can take advantage of these instructions...

Page 408: ...n The Push instruction stores the contents of a specified register in the stack The instruction pre decrements the Stack Pointer to the next avail able location in the stack first Push and Push Multip...

Page 409: ...popping RETI disables the interrupt system Pushing the Stack Pointer is meaningless since it cannot be retrieved from the stack Using the Stack Pointer as the destination of a pop instruction as in t...

Page 410: ...BF53x BF56x Blackfin Processor Programming Reference Parallel Issue This instruction cannot be issued in parallel with other instructions Example sp r0 sp r1 sp p0 sp i0 Also See SP Push Multiple SP...

Page 411: ...struction saves the contents of multiple data and or Pointer registers to the stack The range of registers to be saved always includes the highest index register R7 and or P5 plus any contiguous lower...

Page 412: ...it is advisable that a runtime system be defined to have its compiler scratch registers as the low est indexed registers For instance data registers R0 P0 would be the return value registers for a si...

Page 413: ...nstruction If an unaligned memory access occurs an exception is generated and the instruction aborts as described above Only pointer registers P5 0 can be operands for this instruction SP and FP canno...

Page 414: ...eated here for user convenience a Syntax Terminology mostreg I3 0 M3 0 B3 0 L3 0 A0 X A0 W A1 X A1 W ASTAT RETS RETI RETX RETN RETE LC0 LC1 LT0 LT1 LB0 LB1 USP SEQSTAT and SYSCFG Dreg R7 0 Preg P5 0 F...

Page 415: ...ration is issued the value pointed to by the Stack Pointer is transferred and the SP is replaced by SP 4 The illustration below shows what the stack would look like when a pop such as R3 SP occurs hig...

Page 416: ...ion aborts A value cannot be popped off the stack directly into the Stack Pointer SP SP is an invalid instruction Refer to Register Names on page 1 13 for more information Flags Affected The ASTAT SP...

Page 417: ...l Example r0 sp Load Data Register instruction p4 sp Load Pointer Register instruction i1 sp Pop instruction reti sp Pop instruction supervisor mode required Also See Load Pointer Register Load Data R...

Page 418: ...nal Description The Pop Multiple instruction restores the contents of multiple data and or Pointer registers from the stack The range of registers to be restored always includes the highest index regi...

Page 419: ...shing and the increment operation is used for popping values The Stack Pointer always points to the last used location When a pop operation is issued the value pointed to by the Stack Pointer is trans...

Page 420: ...ntil another push instruc tion overwrites it Of course the usual intent for Pop Multiple is to recover register values that were previously pushed onto the stack The user must exercise pro gramming di...

Page 421: ...example a load store operation might cause a pro tection violation while Pop Multiple is executing In that case SP is reset to its original value prior to the execution of this instruction This mea s...

Page 422: ...e Parallel Issue This instruction cannot be issued in parallel with other instructions Example p5 4 sp P3 through P0 excluded r7 2 sp R1 through R0 excluded r7 5 p5 0 sp D registers R4 through R0 opti...

Page 423: ...uction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Linkage instruction controls the stack frame space on the stack and the Frame Pointer FP for that...

Page 424: ...them Of course FP must not be modified by user code between LINK and UNLINK to preserve stack integrity Neither LINK nor UNLINK can be interrupted However exceptions that occur while either of these i...

Page 425: ...it aligned to use this instruction If an unaligned memory access occurs an exception is generated and the instruction aborts as described above AFTER LINK EXECUTES Saved RETS Prior FP FP Allocated wor...

Page 426: ...ssued in parallel with other instructions Example link 8 establish frame with 8 words allocated for local variables sp r7 0 p5 0 save D and P registers r7 0 p5 0 sp restore D and P registers unlink cl...

Page 427: ...CC on page 11 15 Instruction Overview This chapter discusses the instructions that affect the Control Code CC bit in the ASTAT register Users can take advantage of these instructions to set the CC bi...

Page 428: ...Dreg Dreg less than register signed a CC Dreg imm3 less than immediate signed a CC Dreg Dreg less than or equal register signed a CC Dreg imm3 less than or equal immediate signed a CC Dreg Dreg IU le...

Page 429: ...conditional branching The various forms of the Compare Data Register instruction perform 32 bit signed compare operations on the input operands or an unsigned compare operation if the IU optional mod...

Page 430: ...arry cleared if no carry All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more informatio...

Page 431: ...it Management If r0 0x8FFF FFFF and r3 0x0000 0001 then the unsigned operation cc r0 r3 iu produces CC 0 because r0 is treated as a large unsigned value cc r1 0x7 iu cc r2 r0 iu cc r3 2 iu Also See Co...

Page 432: ...Preg less than register signed a CC Preg imm3 less than immediate signed a CC Preg Preg less than or equal register signed a CC Preg imm3 less than or equal immediate signed a CC Preg Preg IU less tha...

Page 433: ...ion perform 32 bit signed compare operations on the input operands or an unsigned compare operation if the IU optional mode is appended The compare opera tions perform a subtraction and discard the re...

Page 434: ...56x Blackfin Processor Programming Reference Example cc p3 p2 cc p0 1 cc p0 p3 cc p2 4 cc p1 p0 cc p4 3 cc p5 p3 iu cc p1 0x7 iu cc p2 p0 iu cc p3 2 iu Also See Compare Data Register Compare Accumulat...

Page 435: ...e CC bit based on a comparison of two values The input operands are Accumulators These instructions perform 40 bit signed compare operations on the Accumulators The compare operations perform a subtra...

Page 436: ...result is negative cleared if non negative AC0 is set if result generated a carry cleared if no carry All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags op...

Page 437: ...BF53x BF56x Blackfin Processor Programming Reference 11 11 Control Code Bit Management Example cc a0 a1 cc a0 a1 cc a0 a1 Also See Compare Pointer Compare Data Register IF CC JUMP Special Applications...

Page 438: ...s bit equals status bit OR CC a statbit CC status bit equals status bit AND CC a statbit CC status bit equals status bit XOR CC a CC Dreg CC set if the register is non zero a CC statbit CC equals stat...

Page 439: ...t is if the register is non zero Otherwise the operation clears the CC bit Some versions of this instruction logically set or clear an arithmetic status bit based on the status of the Control Code The...

Page 440: ...User Supervisor Instruction Length In the syntax comment a identifies 16 bit instruction length Parallel Issue This instruction cannot be issued in parallel with other instructions Example r0 cc az c...

Page 441: ...inverts the logical state of CC Flags Affected CC is toggled from its previous value by the Negate CC instruction All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and s...

Page 442: ...Instruction Overview 11 16 ADSP BF53x BF56x Blackfin Processor Programming Reference Example cc cc Also See Move CC Special Applications None...

Page 443: ...e s Complement on page 12 4 OR on page 12 6 Exclusive OR on page 12 8 BXORSHIFT BXOR on page 12 10 Instruction Overview This chapter discusses the instructions that specify logical operations Users ca...

Page 444: ...ion The AND instruction performs a 32 bit bit wise logical AND operation on the two source registers and stores the results into the dest_reg The instruction does not implicitly modify the source regi...

Page 445: ...ocessor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode Us...

Page 446: ...cription The NOT One s Complement instruction toggles every bit in the 32 bit register The instruction does not implicitly modify the src_reg The dest_reg and src_reg can be the same D register Using...

Page 447: ...as fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Superv...

Page 448: ...tion The OR instruction performs a 32 bit bit wise logical OR operation on the two source registers and stores the results into the dest_reg The instruction does not implicitly modify the source regis...

Page 449: ...fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Superviso...

Page 450: ...e Exclusive OR XOR instruction performs a 32 bit bit wise logical exclusive OR operation on the two source registers and loads the results into the dest_reg The XOR instruction does not implicitly mod...

Page 451: ...has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supe...

Page 452: ...Type I Without Feedback Dreg_lo CC BXORSHIFT A0 Dreg b Dreg_lo CC BXOR A0 Dreg b LFSR Type I With Feedback Dreg_lo CC BXOR A0 A1 CC b A0 BXORSHIFT A0 A1 CC b Syntax Terminology Dreg R7 0 Dreg_lo R7 0...

Page 453: ...ifted into A0 In the following circuits describing the BXOR instruction group a bit wise XOR reduction is defined as where B0 through BN 1 represent the N bits that result from masking the contents of...

Page 454: ...a bit wise XOR of A0 logically AND ed with a dreg The result of the operation is placed into both the CC flag and the least significant bit of the destination register The operation is shown in Figur...

Page 455: ...ccumulator A0 is not modified by this operation This operation is illustrated in Figure 12 3 The upper 15 bits of dreg_lo are overwritten with zero and dr 0 IN after the operation Modified Type I LFSR...

Page 456: ...cond instruction in this class performs a bit wise XOR of A0 logi cally AND ed with A1 The resulting intermediate bit is XOR ed with the CC flag The result of the operation is placed into both the CC...

Page 457: ...he feedback version of the BXORSHIFT instruction affects no flags All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Bla...

Page 458: ...llel Instructions on page 20 1 Example r0 l cc bxorshift a0 r1 r0 l cc bxor a0 r1 r0 l cc bxor a0 a1 cc a0 bxorshift a0 a1 cc Also See None Special Applications Linear feedback shift registers LFSRs c...

Page 459: ...XTRACT on page 13 16 BITMUX on page 13 21 ONES One s Population Count on page 13 26 Instruction Overview This chapter discusses the instructions that specify bit operations Users can take advantage of...

Page 460: ...6 bit instruction length Functional Description The Bit Clear instruction clears the bit designated by bit_position in the specified D register It does not affect other bits in that register The bit_p...

Page 461: ...mily products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instru...

Page 462: ...ment a identifies 16 bit instruction length Functional Description The Bit Set instruction sets the bit designated by bit_position in the specified D register It does not affect other bits in the D re...

Page 463: ...amily products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instr...

Page 464: ...struction length Functional Description The Bit Toggle instruction inverts the bit designated by bit_position in the specified D register The instruction does not affect other bits in the D register T...

Page 465: ...ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instructions Example bittgl r2 24 toggle bit 24...

Page 466: ...of 0 through 31 Instruction Length In the syntax comment a identifies 16 bit instruction length Functional Description The Bit Test instruction sets or clears the CC bit based on the bit desig nated...

Page 467: ...ily products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instruc...

Page 468: ...b Syntax Terminology Dreg R7 0 Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Bit Field Deposit instruction merges the background bit field...

Page 469: ...gth is transparent Sign extended L 0 and p 0 This case loads 0x0000 0000 into dest_reg The sign of a zero length zero position foreground is zero therefore sign extended is all zeros Table 13 1 Input...

Page 470: ...ign extends that number Sign extended L p 32 Any foreground bits that fall outside the range 31 0 are truncated The Bit Field Deposit instruction does not modify the contents of the two source registe...

Page 471: ...visor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instructions on page 20 1 Example Bit Field Deposit Unsigned r7...

Page 472: ...length then the Bit Field Deposit unsigned instruction produces R7 0b1111 1111 1101 1111 0101 1111 1111 1111 Bit Field Deposit Sign Extended r7 deposit r4 r3 x sign extended If R4 0b1111 1111 1111 11...

Page 473: ...the background bit field R3 0b0000 1001 1010 1100 0000 1101 0000 1001 where bits 31 16 are the foreground bit field bits 15 8 are the position and bits 7 0 are the length then the Bit Field Deposit un...

Page 474: ...Dreg Dreg_lo X sign extended b Syntax Terminology Dreg R7 0 Dreg_lo R7 0 L Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Bit Field Extracti...

Page 475: ...ith zeros The Bit Field Extraction instruction does not modify the contents of the two source registers One of the source registers can also serve as dest_reg Options The user has the choice of using...

Page 476: ...uired Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instructions on page 20 1 Example Bit Fiel...

Page 477: ...then the Bit Field Extraction unsigned instruction produces R7 0b0000 0000 0000 0000 0000 0001 0010 1110 Bit Field Extraction Sign Extended r7 extract r4 r3 l x sign extended If R4 0b1010 0101 1010 01...

Page 478: ...s is the scene bit field R3 0bxxxx xxxx xxxx xxxx 0000 1101 0000 1001 where bits bits 15 8 are the position and bits 7 0 are the length Then the Bit Field Extraction sign extended instruction produces...

Page 479: ...dentifies 32 bit instruction length Functional Description The Bit Multiplex instruction merges bit streams The instruction has two versions Shift Right and Shift Left This instruc tion overwrites the...

Page 480: ...he same D register Table 13 3 Contents Before Shift IF 39 32 31 24 23 16 15 8 7 0 source_1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx source_0 yyyy yyyy yyyy yyyy yyyy yyyy yyyy yyyy Accumulator A0 zzzz...

Page 481: ...er Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instructions on page 20 1 Table 13 5 A Shift Left Instr...

Page 482: ...es R2 0b0101 0010 1101 0010 1110 0001 1101 0101 R3 0b0110 0001 1101 0101 0101 0010 1101 0010 A0 0b1000 0000 0000 0000 0000 0000 0000 0000 0000 0001 bitmux r3 r2 a0 asl left shift If R3 0b1010 0101 101...

Page 483: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 13 25 Bit Operations Also See None Special Applications Convolutional encoder algorithms...

Page 484: ...tion Length In the syntax comment b identifies 32 bit instruction length Functional Description The One s Population Count instruction loads the number of 1 s contained in the src_reg into the lower h...

Page 485: ...the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see I...

Page 486: ...Instruction Overview 13 28 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 487: ...Arithmetic Shift on page 14 7 Logical Shift on page 14 14 ROT Rotate on page 14 21 Instruction Overview This chapter discusses the instructions that manipulate bit operations Users can take advantage...

Page 488: ...c_reg 1 dest_reg dest_reg src_reg 2 Syntax Pointer Operations Preg Preg Preg 1 dest_reg dest_reg src_reg x 2 a Preg Preg Preg 2 dest_reg dest_reg src_reg x 4 a Data Operations Dreg Dreg Dreg 1 dest_re...

Page 489: ...dified Flags Affected The D register versions of this instruction affect flags as follows AZ is set if result is zero cleared if nonzero AN is set if result is negative cleared if non negative V is se...

Page 490: ...ackfin Processor Programming Reference Example p3 p3 p2 1 p3 p3 p2 2 p3 p3 p2 2 p3 p3 p2 4 r3 r3 r2 1 r3 r3 r2 2 r3 r3 r2 2 r3 r3 r2 4 Also See Shift with Add Logical Shift Arithmetic Shift Add Multip...

Page 491: ...dder_pntr src_pntr x 4 a Syntax Terminology Preg P5 0 Instruction Length In the syntax comment a identifies 16 bit instruction length Functional Description The Shift with Add instruction combines a o...

Page 492: ...gramming Reference Parallel Issue This instruction cannot be issued in parallel with other instructions Example p3 p0 p3 1 p3 p3 2 p0 p3 p0 p3 2 p3 p3 4 p0 Also See Add with Shift Logical Shift Arithm...

Page 493: ...etic right shift a Dreg uimm5 logical left shift a Dreg_lo_hi Dreg_lo_hi uimm4 arithmetic right shift b Dreg_lo_hi Dreg_lo_hi uimm4 S arithmetic left shift b Dreg Dreg uimm5 arithmetic right shift b D...

Page 494: ...the syntax Instruction Length In the syntax comment a identifies 16 bit instruction length Comment b identifies 32 bit instruction length Functional Description The Arithmetic Shift instruction shift...

Page 495: ...ing or logical non saturating instructions L Logical left shift instructions are duplicated in the Syntax section for programmer convenience See the Logical Shift instruction for details on those oper...

Page 496: ...instruction do not implicitly modify the src_reg values Optionally dest_reg can be the same D register as src_reg Doing this explicitly modifies the source register The Accumulator versions always mo...

Page 497: ...original number See Saturation on page 1 17 for a description of saturation behavior Flags Affected The versions of this instruction that send results to a Dreg set flags as follows AZ is set if resul...

Page 498: ...gs and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issu...

Page 499: ...by r7 l r3 h ashift r0 h by r7 l r3 l ashift r0 l by r7 l r3 l ashift r0 h by r7 l s shift half word saturated r3 h ashift r0 l by r7 l s shift half word saturated r3 h ashift r0 h by r7 l s r3 l ash...

Page 500: ...rc_reg BY shift_magnitude Syntax Pointer Shift Fixed Magnitude Preg Preg 1 right shift by 1 bit a Preg Preg 2 right shift by 2 bit a Preg Preg 1 left shift by 1 bit a Preg Preg 2 left shift by 2 bit a...

Page 501: ...Dreg R7 0 Dreg_lo R7 0 L Dreg_lo_hi R7 0 L R7 0 H Preg P5 0 uimm4 4 bit unsigned field with a range of 0 through 15 uimm5 5 bit unsigned field with a range of 0 through 31 Instruction Length In the sy...

Page 502: ...length providing a separate source and destination register alter native data sizes and parallel issue with Load Store instructions Both syntaxes support constant and registered shift magnitudes For...

Page 503: ...Shift magnitudes that exceed the size of the destination register produce all zeros in the result For example shifting a 16 bit register value by 20 bit places a valid operation produces 0x0000 A shi...

Page 504: ...t is zero cleared if nonzero AN is set if result is negative cleared if non negative AV1 is cleared All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags opera...

Page 505: ...ry r3 h r0 l 12 data left shift half word register r3 h r0 h 14 same as above half word register com binations are arbitrary r3 r6 4 right shift 32 bit word r3 r6 4 left shift 32 bit word a0 a0 7 Accu...

Page 506: ...ruction Overview 14 20 ADSP BF53x BF56x Blackfin Processor Programming Reference Also See Arithmetic Shift ROT Rotate Shift with Add Vector Arithmetic Shift Vector Logical Shift Special Applications N...

Page 507: ...egistered Rotate Magnitude Dreg ROT Dreg BY Dreg_lo b A0 ROT A0 BY Dreg_lo b A1 ROT A1 BY Dreg_lo b Syntax Terminology Dreg R7 0 imm6 6 bit signed field with a range of 32 through 31 Instruction Lengt...

Page 508: ...posite end of the register If 31 0 D register 1010 1111 0000 0000 0000 0000 0001 1010 CC bit N 1 or 0 Rotate left 1 bit 31 0 D register 0101 1110 0000 0000 0000 0000 0011 010N CC bit 1 Rotate left 1 b...

Page 509: ...it rearranges them in a circular fashion However the last bit rotated out of the register remains in the CC bit and is not returned to the register Because rotates are performed all at once and not o...

Page 510: ...erently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issu...

Page 511: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 14 25 Shift Rotate Operations Also See Arithmetic Shift Logical Shift Special Applications None...

Page 512: ...Instruction Overview 14 26 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 513: ...on page 15 13 Add Immediate on page 15 16 DIVS DIVQ Divide Primitive on page 15 19 EXPADJ on page 15 26 MAX on page 15 30 MIN on page 15 32 Modify Decrement on page 15 34 Modify Increment on page 15...

Page 514: ...page 15 77 Saturate on page 15 80 SIGNBITS on page 15 83 Subtract on page 15 86 Subtract Immediate on page 15 90 Instruction Overview This chapter discusses the instructions that specify arithmetic o...

Page 515: ...Arithmetic Operations ABS General Form dest_reg ABS src_reg Syntax A0 ABS A0 b A0 ABS A1 b A1 ABS A0 b A1 ABS A1 b A1 ABS A1 A0 ABS A0 b Dreg ABS Dreg b Syntax Terminology Dreg R7 0 Instruction Lengt...

Page 516: ...n the destination Saturation is automatically performed with the instruction so taking the absolute value of the larg est magnitude negative number returns the largest magnitude positive number The AB...

Page 517: ...ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Para...

Page 518: ...support but shorter instruction length a Dreg Dreg Dreg sat_flag saturation optionally sup ported but at the cost of longer instruction length b Data Registers 16 Bit Operands 16 Bit Result Dreg_lo_hi...

Page 519: ...n can sometimes save execution time because it can be issued in parallel with certain other instructions See Parallel Issue on page 15 5 The D register version that accepts 16 bit half word operands s...

Page 520: ...therwise All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF...

Page 521: ...r0 l 0x7000 and r7 l 0x2000 then r4 l r0 l r7 l ns produces r4 l 0x9000 because no saturation is enforced If r0 l 0x7000 and r7 h 0x2000 then r4 l r0 l r7 h s produces r4 l 0x7FFF satu rated to the m...

Page 522: ...0 Dreg_lo_hi R7 0 L R7 0 H Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Add Subtract Prescale Down instruction combines two 32 bit val ues...

Page 523: ...und ing behavior Flags Affected The following flags are affected by this instruction AZ is set if result is zero cleared if nonzero AN is set if result is negative cleared if non negative V is cleared...

Page 524: ...fin Processor Programming Reference Also See Add Subtract Prescale Up RND Round to Half Word Add Special Applications Typically use the Add Subtract Prescale Down instruction to provide an IEEE 1180 c...

Page 525: ...R7 0 Dreg_lo_hi R7 0 L R7 0 H Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Add Subtract Prescale Up instruction combines two 32 bit value...

Page 526: ...behavior Flags Affected The following flags are affected by this instruction AZ is set if result is zero cleared if nonzero AN is set if result is negative cleared if non negative V is set if result s...

Page 527: ...ference 15 15 Arithmetic Operations Also See RND Round to Half Word Add Subtract Prescale Down Add Special Applications Typically use the Add Subtract Prescale Up instruction to provide an IEEE 1180 c...

Page 528: ...ntax Terminology Dreg R7 0 Preg P5 0 SP FP Ireg I3 0 imm7 7 bit signed field with the range of 64 through 63 Instruction Length In the syntax comment a identifies 16 bit instruction length Functional...

Page 529: ...ware clears all the circular address buffer registers during boot up to dis able circular buffering then initializes them later if needed Flags Affected D register versions of this instruction set fla...

Page 530: ...truction can be issued in parallel with specific other instructions For details see Issuing Parallel Instruc tions on page 20 1 The Data Register and Pointer Register versions of this instruction cann...

Page 531: ...idend Then set the AQ flag based on the MSBs of the 32 bit dividend and the 16 bit divisor Left shift the dividend one bit Copy the logical inverse of AQ into the dividend LSB a Syntax Terminology Dre...

Page 532: ...ssuing 16 DIVQ instructions Less quotient resolution is produced by executing fewer DIVQ iterations The result of each successive addition or subtraction appears in dividend_register aligned and ready...

Page 533: ...s to the right of the binal point of the dividend numerator DL represent the number of bits to the left of the binal point of the divisor and DR represent the number of bits to the right of the binal...

Page 534: ...its the usable dividend range to 31 bits Viola tions of this range produce an invalid result of the division operation The algorithm overflows if the result cannot be represented in the format of the...

Page 535: ...ands decreases their resolution and may introduce one LSB of error in the quotient Such error can be detected and corrected by the following steps Save the original unscaled dividend and divisor in sc...

Page 536: ...y products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instructi...

Page 537: ...kfin Processor Programming Reference 15 25 Arithmetic Operations r0 r0 l x Sign extend the 16 bit quotient to 32bits r0 contains the quotient 70 5 14 Also See LSETUP LOOP Multiply 32 Bit Operands Spec...

Page 538: ...eg_lo_hi R7 0 L R7 0 H Dreg_lo R7 0 L Dreg R7 0 Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Exponent Detection instruction identifies the...

Page 539: ...id range of exponents is 0 through 31 with 31 representing the smallest 32 bit number magnitude and 15 representing the smallest 16 bit number magnitude Exponent Detection supports three types of samp...

Page 540: ...s 24 Assume R4 0xF000 0052 and R2 L 27 Then R5 L becomes 3 r5 l expadj r4 l r2 l Assume R4 L 0x0765 and R2 L 12 Then R5 L becomes 4 Assume R4 L 0xC765 and R2 L 12 Then R5 L becomes 1 r5 l expadj r4 h...

Page 541: ...rations Special Applications EXPADJ detects the exponent of the largest magnitude number in an array The detected value may then be used to normalize the array on a subse quent pass with a shift opera...

Page 542: ...the maximum or most positive value of the source registers The operation subtracts src_reg_1 from src_reg_0 and selects the output based on the signs of the input values and the arith metic flags The...

Page 543: ...s flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instr...

Page 544: ...regis ters to the dest_reg The minimum value of the source registers is the value closest to The operation subtracts src_reg_1 from src_reg_0 and selects the output based on the signs of the input val...

Page 545: ...BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Par...

Page 546: ...src_reg dec rement and saturate the result at 32 bits sign extended b 32 Bit Registers Preg Preg dest_reg_new dest_reg_old src_reg a Ireg Mreg dest_reg_new dest_reg_old src_reg a Syntax Terminology P...

Page 547: ...egisters Index Length and Base are not initialized automatically by Reset Traditionally user software clears all the circular address buffer registers during boot up to dis able circular buffering the...

Page 548: ...16 bit instructions For details see Issuing Parallel Instructions on page 20 1 All other 16 bit versions of this instruction cannot be issued in parallel with other instructions Example a0 a1 a0 a1 w...

Page 549: ...32 bits sign extended b 32 Bit Registers Preg Preg BREV dest_reg_new dest_reg_old src_reg bit reversed carry only a Ireg Mreg opt_brev dest_reg_new dest_reg_old src_reg optional bit reverse a Dreg A0...

Page 550: ...n length Comment b identifies 32 bit instruction length Functional Description The Modify Increment instruction increments a register by a user defined quantity In some versions the instruction copies...

Page 551: ...y clear Lreg beforehand can result in unexpected Ireg values The circular address buffer registers Index Length and Base are not initialized automatically by Reset Traditionally user software clears a...

Page 552: ...V is set unaffected otherwise AV0 is set if result saturates and the dest_reg is A0 cleared if no saturation AV0S is set if AV0 is set unaffected otherwise All other flags are unaffected The versions...

Page 553: ...he Pointer Register Index Register and Modify Register versions of the instruction do not affect the flags Required Mode User Supervisor Parallel Issue The 32 bit versions of this instruction and the...

Page 554: ...sor Programming Reference Also See Modify Decrement Add Shift with Add Special Applications Typically use the Index Register and Pointer Register versions of the Modify Increment instruction to increm...

Page 555: ...it result b Multiply And Accumulate Unit 1 MAC1 Dreg_hi Dreg_lo_hi Dreg_lo_hi opt_mode_1 16 bit result into the destination upper half word register b Dreg_odd Dreg_lo_hi Dreg_lo_hi opt_mode_2 32 bit...

Page 556: ...erations performed by the Multiply and Accumulate Unit 0 MAC0 portion of the architecture load their 16 bit results into the lower half of the destination data register 32 bit results go into an even...

Page 557: ...description of saturation behavior See Rounding and Truncating on page 1 19 for a description of round ing behavior The versions of this instruction that produce 32 bit results do not perform rounding...

Page 558: ...n in desti nation register half Result is between minimum 0 and maximum 1 2 16 or expressed in hex between minimum 0x0000 and maximum 0xFFFF Unsigned fraction Multiply 0 16 0 16 to produce 0 32 result...

Page 559: ...o rounding Saturate the result to 0 16 precision in destination register half Result is between minimum 0 and maximum 1 2 16 or expressed in hex between minimum 0x0000 and maximum 0xFFFF Not applicabl...

Page 560: ...extract Mul tiply 16 0 16 0 to produce 32 0 results No shift correction Round 32 0 format value at bit 16 RND_MOD bit in the ASTAT register controls the rounding Saturate to 32 0 result Extract the u...

Page 561: ...me flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This in...

Page 562: ...Reference Also See Multiply 32 Bit Operands Multiply and Multiply Accumulate to Accu mulator Multiply and Multiply Accumulate to Half Register Multiply and Multiply Accumulate to Data Register Vector...

Page 563: ...instruction mimics multiplication in the C language and effectively performs Dreg1 Dreg1 Dreg2 modulo 232 Since the integer multiply is modulo 232 the result always fits in a 32 bit dest_reg and overf...

Page 564: ...teger and X n 1 is the result that can be multiplied again to further the pseudo random sequence Flags Affected None Required Mode User Supervisor Parallel Issue This instruction cannot be issued in p...

Page 565: ...hi opt_mode multiply and add b A0 Dreg_lo_hi Dreg_lo_hi opt_mode multiply and subtract b Multiply And Accumulate Unit 1 MAC1 Operations A1 Dreg_lo_hi Dreg_lo_hi opt_mode multiply and store b A1 Dreg_l...

Page 566: ...ds of both MACs as signed fractions with left shift correction as required Options The Multiply and Multiply Accumulate to Accumulator instruction sup ports the following options Saturation is support...

Page 567: ...inimum 0x00 0000 0000 through maximum 0xFF FFFF FFFF IS Signed integer Multiply 16 0 x 16 0 to produce 32 0 format data Perform no shift correction Sign extend the result to 40 0 format before passing...

Page 568: ...et unaffected otherwise All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information...

Page 569: ...rands Multiply and Mul tiply Accumulate to Half Register Multiply and Multiply Accumulate to Data Register Vector Multiply Vector Multiply and Multiply Accumulate Special Applications DSP filter appli...

Page 570: ...ly And Accumulate Unit 0 MAC0 Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi opt_mode mul tiply and store b Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi opt_mode multi ply and add b Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi opt_mode mu...

Page 571: ...t 16 bits of the Accumulator into a data half register The fraction versions of this instruction the default and FU options transfer the Accumulator result to the destination register according to the...

Page 572: ...A0 L A0 H A0 X Destination Register XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX A1 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX A0 L A0 H A0 X Destination Register XXXX XXXX XXXX XXXX XXXX XXXX XXXX...

Page 573: ...r round Accumulator 9 31 format value at bit 16 RND_MOD bit in the ASTAT register controls the rounding Saturate the result to 1 15 precision and copy it to the destination register half Result is bet...

Page 574: ...nimum 0x00 0000 0000 and maximum 0xFF FFFF FFFF Extract the lower 16 bits of the Accumulator Saturate for 16 0 precision and copy to the destination register half Result is between minimum 0 and maxim...

Page 575: ...9 31 format before copying or accumulating to Accumu lator Then saturate Accumulator to maintain 9 31 precision Accumulator result is between minimum 0x80 0000 0000 and maximum 0x7F FFFF FFFF To extr...

Page 576: ...umulator result is between minimum 0x00 8000 0000 and maximum 0x00 7FFF FFFF To extract to half register round Accumulator 40 0 format value at bit 16 RND_MOD bit in the ASTAT register controls the ro...

Page 577: ...t unaffected otherwise AV1 is set if result in Accumulator A1 MAC1 operation saturates cleared if A1 result does not saturate AV1S is set if AV1 is set unaffected otherwise All other flags are unaffec...

Page 578: ...rands are unsigned fractions Add the product into A1 then copy to r3 h Also See Multiply 32 Bit Operands Multiply and Multiply Accumulate to Accu mulator Multiply and Multiply Accumulate to Data Regis...

Page 579: ...Unit 0 MAC0 Dreg_even A0 Dreg_lo_hi Dreg_lo_hi opt_mode mul tiply and store b Dreg_even A0 Dreg_lo_hi Dreg_lo_hi opt_mode multiply and add b Dreg_even A0 Dreg_lo_hi Dreg_lo_hi opt_mode multiply and s...

Page 580: ...Accumulator into a data register The 32 bits are saturated at 32 bits The Multiply and Accumulate Unit 0 MAC0 portion of the architecture performs operations that involve Accumulator A0 it loads the...

Page 581: ...turate the result to 0 32 precision and copy it to the destination regis ter Result is between minimum 0 and maximum 1 2 32 or expressed in hex between minimum 0x0000 0000 and maximum 0xFFFF FFFF IS S...

Page 582: ...te Accumulator to maintain 40 0 precision Accumulator result is between minimum 0x80 0000 0000 and maximum 0x7F FFFF FFFF To extract shift the Accumulator contents one place to the left multiply x 2 s...

Page 583: ...t unaffected otherwise AV1 is set if result in Accumulator A1 MAC1 operation saturates cleared if A1 result does not saturate AV1S is set if AV1 is set unaffected otherwise All other flags are unaffec...

Page 584: ...n into r3 Also See Move Register Move Register Half Multiply 32 Bit Operands Multiply and Multiply Accumulate to Accumulator Multiply and Multiply Accu mulate to Half Register Vector Multiply Vector M...

Page 585: ...imulta neously in one 32 bit length instruction b Syntax Terminology Dreg R7 0 sat_flag nonoptional saturation flag S or NS Instruction Length In the syntax comment a identifies 16 bit instruction len...

Page 586: ...he result NS no saturation See Saturation on page 1 17 for a description of saturation behavior Flags Affected This instruction affects the flags as follows AZ is set if result is zero cleared if nonz...

Page 587: ...equent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue The 32 bit versions of this instruction can b...

Page 588: ...Instruction Overview 15 76 ADSP BF53x BF56x Blackfin Processor Programming Reference Also See Vector Negate Two s Complement Special Applications None...

Page 589: ...it normalized frac tion number into a 16 bit normalized fraction number by extracting and saturating bits 31 16 then discarding bits 15 0 The instruction supports only biased rounding which adds a hal...

Page 590: ...lags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see...

Page 591: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 15 79 Arithmetic Operations Also See Add Add Subtract Prescale Up Add Subtract Prescale Down Special Applications None...

Page 592: ...Accumula tors at the 32 bit boundary b Syntax Terminology None Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Saturate instruction saturate...

Page 593: ...es and the dest_reg is A0 cleared if no overflow AV0S is set if AV0 is set unaffected otherwise AV1 is set if result saturates and the dest_reg is A1 cleared if no overflow AV1S is set if AV1 is set u...

Page 594: ...truction Overview 15 82 ADSP BF53x BF56x Blackfin Processor Programming Reference Example a0 a0 s a1 a1 s a1 a1 s a0 a0 s Also See Subtract saturate options Add saturate options Special Applications N...

Page 595: ..._hi R7 0 L R7 0 H Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Sign Bit instruction returns the number of sign bits in a number and can be...

Page 596: ...of the SIGNBITS instruction can be used directly as the argu ment to ASHIFT to normalize the number Resultant numbers will be in the following formats S signbit M magnitude bit In addition the SIGNBIT...

Page 597: ...or details see Issuing Parallel Instructions on page 20 1 Example r2 l signbits r7 r1 l signbits r5 l r0 l signbits r4 h r6 l signbits a0 r5 l signbits a1 Also See EXPADJ Special Applications You can...

Page 598: ...sup ported but at the cost of longer instruction length b 16 Bit Operands 16 Bit Result Dreg_lo_hi Dreg_lo_hi Dreg_lo_hi sat_flag b Syntax Terminology Dreg R7 0 Dreg_lo_hi R7 0 L R7 0 H sat_flag nonop...

Page 599: ...e half word data register operands and store the result in a half word data register All the instructions for 16 bit data are 32 bit instruction length In the syntax where sat_flag appears substitute...

Page 600: ...ue The 32 bit versions of this instruction can be issued in parallel with spe cific other 16 bit instructions For details see Issuing Parallel Instructions on page 20 1 The 16 bit versions of this ins...

Page 601: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 15 89 Arithmetic Operations Also See Modify Decrement Vector Add Subtract Special Applications None...

Page 602: ...ntax comment a identifies 16 bit instruction length Functional Description The Subtract Immediate instruction subtracts a constant value from an Index register without saturation L The instruction ver...

Page 603: ...y Reset Traditionally user software clears all the circular address buffer registers during boot up to dis able circular buffering then initializes them later if needed To subtract immediate values fr...

Page 604: ...Instruction Overview 15 92 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 605: ...on page 16 3 Core Synchronize on page 16 5 System Synchronize on page 16 8 EMUEXCPT Force Emulation on page 16 11 Disable Interrupts on page 16 13 Enable Interrupts on page 16 15 RAISE Force Interrup...

Page 606: ...e state The Core Synchronize instruction resolves all pending operations and flushes the core store buffer before proceeding to the next instruction The Sys tem Synchronize instruction forces all spec...

Page 607: ...clock frequencies The IDLE instruction requests an idle state by setting the idle_req bit in SEQSTAT register Setting the idle_req bit precedes placing the Blackfin processor in a quiescent state If y...

Page 608: ...nstruction executes only in Supervisor mode If execution is attempted in User mode the instruction produces an Illegal Use of Pro tected Resource exception Parallel Issue This instruction cannot be is...

Page 609: ...ronize CSYNC instruction ensures resolution of all pend ing core operations and the flushing of the core store buffer before proceeding to the next instruction Pending core operations include any spec...

Page 610: ...processing before CSYNC completes Also See System Synchronize Special Applications Use CSYNC to enforce a strict execution sequence on loads and stores or to conclude all transitional core states bef...

Page 611: ...lly allows loads to access memory speculatively The core may later cancel or restart speculative loads By using the Core Synchro nize or System Synchronize instructions and managing interrupts appropr...

Page 612: ...SSYNC flushes any write buffers between the L1 memory and the system interface and generates a Synch request signal to the external system The operation requires an acknowledgement Synch_Ack signal by...

Page 613: ...ollowing example code sequence if cc jump away_from_here produces speculative branch prediction ssync r0 p0 load In this example SSYNC ensures that the load instruction will not be exe cuted speculati...

Page 614: ...the following instruction sequence is typical instruction instruction CLI r0 disable interrupts idle enable Idle state ssync conclude all speculative states assert external Sync signal await Synch_Ack...

Page 615: ...truction forces an emulation exception thus allowing the processor to enter emulation mode When emulation is enabled the processor immediately takes an exception into emulation mode When emulation is...

Page 616: ...Instruction Overview 16 12 ADSP BF53x BF56x Blackfin Processor Programming Reference Example emuexcpt Also See RAISE Force Interrupt Reset Special Applications None...

Page 617: ...rrupts instruction globally disables general interrupts by setting IMASK to all zeros In addition the instruction copies the previous contents of IMASK into a user specified register in order to save...

Page 618: ...r Programming Reference Parallel Issue The Disable Interrupts instruction cannot be issued in parallel with other instructions Example cli r3 Also See Enable Interrupts Special Applications This instr...

Page 619: ...tion length Functional Description The Enable Interrupts instruction globally enables interrupts by restoring the previous state of the interrupt system back into IMASK Flags Affected None Required Mo...

Page 620: ...BF56x Blackfin Processor Programming Reference Example sti r3 Also See Disable Interrupts Special Applications This instruction is often located after an IDLE instruction so that it will execute afte...

Page 621: ...uction forces a specified interrupt or reset to occur Typically it is a software method of invoking a hardware event for debug purposes When the RAISE instruction is issued the processor sets a bit in...

Page 622: ...ion EMU events use the EXCPT and EMUEXCPT instructions respectively for those events The RAISE instruction does not take effect before the write back stage in the pipeline Flags Affected None 3 reserv...

Page 623: ...ecution is attempted in User mode the Force Interrupt Reset instruction produces an Illegal Use of Protected Resource exception Parallel Issue The Force Interrupt Reset instruction cannot be issued in...

Page 624: ...ax comment a identifies 16 bit instruction length Functional Description The Force Exception instruction forces an exception with code uimm4 When the EXCPT instruction is issued the sequencer vectors...

Page 625: ...in Processor Programming Reference 16 21 External Event Management Parallel Issue The Force Exception instruction cannot be issued in parallel with other instructions Example excpt 4 Also See None Spe...

Page 626: ...lly zero the instruction sets the CC bit If the byte is originally nonzero the instruction clears the CC bit The sequence of this memory transaction is atomic TESTSET accesses the entire logical memor...

Page 627: ...ET com pletes the TESTSET sequence cannot be interrupted For example any exceptions associated with the CPLB lookup for both the load and store operations must be completed before the load of the TEST...

Page 628: ...structions Example testset p1 The TESTSET instruction may be preceded by a CSYNC or SSYNC instruction to ensure that all previous exceptions or interrupts have been processed before the atomic operati...

Page 629: ...t instruction length Functional Description The No Op instruction increments the PC and does nothing else Typically the No Op instruction allows previous instructions time to complete before continuin...

Page 630: ...with spe cific other instructions For details see Issuing Parallel Instructions on page 20 1 Example nop mnop mnop a 16 bit instr a 16 bit instr Also See None Special Applications MNOP can be used to...

Page 631: ...can be used to improve performance by initiating a data cache line fill in advance of when the desired data is actually required for processing The FLUSH instruction is useful when data cache is conf...

Page 632: ...has been defined as cacheable By invalidating the cache lines associated with the buffer coherency is maintained between the contents stored in cache and the actual values in source memory When the bu...

Page 633: ...ed with the effective address in the P register The operation causes the line to be fetched if it is not currently in the data cache and if the address is cacheable that is if bit CPLB_L1_CHBL 1 If th...

Page 634: ...ackfin Processor Programming Reference Flags Affected None Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instructions Example prefetch p2 prefet...

Page 635: ...elects the cache line corresponding to the effective address contained in the P register If the cached data line is dirty the instruction writes the line out and marks the line clean in the data cache...

Page 636: ...Blackfin Processor Programming Reference Flags Affected None Required Mode User Supervisor Parallel Issue The instruction cannot be issued in parallel with other instructions Example flush p2 flush p...

Page 637: ...inval idate a specific line in the cache The contents of the P register specify the line to invalidate If the line is in the cache and dirty the cache line is written out to the next level of memory...

Page 638: ...sor Programming Reference Flags Affected None Required Mode User Supervisor Parallel Issue The Data Cache Line Invalidate instruction cannot be issued in parallel with other instructions Example flush...

Page 639: ...uses the instruction cache to invalidate a specific line in the cache The contents of the P register spec ify the line to invalidate The instruction cache contains no dirty bit Consequently the conten...

Page 640: ...Blackfin Processor Programming Reference Flags Affected None Required Mode User Supervisor Parallel Issue This instruction cannot be issued in parallel with other instructions Example iflush p2 iflush...

Page 641: ...p on page 18 8 Dual 16 Bit Accumulator Extraction with Addition on page 18 13 BYTEOP16P Quad 8 Bit Add on page 18 15 BYTEOP1P Quad 8 Bit Average Byte on page 18 19 BYTEOP2P Quad 8 Bit Average Half Wor...

Page 642: ...tion Overview This chapter discusses the instructions that manipulate video pixels Users can take advantage of these instructions to align bytes disable exceptions that result from misaligned 32 bit m...

Page 643: ...ngth In the syntax comment b identifies 32 bit instruction length Functional Description The Byte Align instruction copies a contiguous four byte unaligned word from a combination of two data register...

Page 644: ...ags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruc...

Page 645: ...nce 18 5 Video Pixel Operations Example If r3 0xABCD 1234 and r4 0xBEEF DEAD then r0 align8 r3 r4 produces r0 0x34BE EFDE r0 align16 r3 r4 produces r0 0x1234 BEEF and r0 align24 r3 r4 produces r0 0xCD...

Page 646: ...xceptions that would otherwise be caused by misaligned 32 bit memory loads issued in parallel This instruction only affects misaligned 32 bit load instructions that use I register indirect addressing...

Page 647: ...reg load Also See Any Quad 8 Bit instructions ALIGN8 ALIGN16 ALIGN24 Special Applications Use the DISALGNEXCPT instruction when priming data registers for Quad 8 Bit single instruction multiple data...

Page 648: ...es b Dreg BYTEOP3P Dreg_pair Dreg_pair HI sum into high bytes b reverse byte order operands Dreg BYTEOP3P Dreg_pair Dreg_pair LO R sum into low bytes b Dreg BYTEOP3P Dreg_pair Dreg_pair HI R sum into...

Page 649: ...erformed as a signed operation The 16 bit operand is sign extended to 32 bits before adding The only valid input source register pairs are R1 0 and R3 2 Table 18 2 Assuming the source registers contai...

Page 650: ...ssuming a source register pair contains the following This instruction prevents exceptions that would otherwise be caused by misaligned 32 bit memory loads issued in parallel Options The R syntax reve...

Page 651: ...byte ordering Assume a source register pair contains the data shown in Table 18 6 Flags Affected None Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with spec...

Page 652: ...3p r1 0 r3 2 lo r r3 byteop3p r1 0 r3 2 hi r Also See BYTEOP16P Quad 8 Bit Add Special Applications This instruction is primarily intended for video motion compensation algorithms The instruction supp...

Page 653: ...tion Length In the syntax comment b identifies 32 bit instruction length Functional Description The Dual 16 Bit Accumulator Extraction with Addition instruction adds together the upper half words bits...

Page 654: ...6 bit instructions For details see Issuing Parallel Instructions on page 20 1 Example r4 a1 l a1 h r7 a0 l a0 h Also See SAA Quad 8 Bit Subtract Absolute Accumulate Special Applications Use the Dual 1...

Page 655: ...rder operands Dreg Dreg BYTEOP16P Dreg_pair Dreg_pair R b Syntax Terminology Dreg R7 0 Dreg_pair R1 0 R3 2 only Instruction Length In the syntax comment b identifies 32 bit instruction length Function...

Page 656: ...llustrated below In the default source order case for example not the R syntax assume that a source register pair contains the data shown in Table 18 9 This instruction prevents exceptions that would...

Page 657: ...ing Assume a source register pair contains the data shown in Table 18 10 The mnemonic derives its name from the fact that the operands are bytes the result is 16 bits and the arithmetic operation is p...

Page 658: ...ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuin...

Page 659: ...Dreg_pair T truncated b reverse byte order operands Dreg BYTEOP1P Dreg_pair Dreg_pair R b Dreg BYTEOP1P Dreg_pair Dreg_pair T R truncated b Syntax Terminology Dreg R7 0 Dreg_pair R1 0 R3 2 only Instru...

Page 660: ...no bearing on the rounding behavior of this instruction The only valid input source register pairs are R1 0 and R3 2 The Quad 8 Bit Average Byte instruction provides byte alignment directly in the so...

Page 661: ...e caused by misaligned 32 bit memory loads issued in parallel Options The Quad 8 Bit Average Byte instruction supports the following options Table 18 13 I register Bits and the Byte Alignment The byte...

Page 662: ...rmance applications cannot afford the overhead of reloading both register pair operands to maintain byte order for every calculation Instead they alternate and load only one register pair operand each...

Page 663: ...ee Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instructions o...

Page 664: ...eg_1 TL R dest_reg BYTEOP2P src_reg_0 src_reg_1 TH R Syntax forward byte order operands Dreg BYTEOP2P Dreg_pair Dreg_pair RNDL round into low bytes b Dreg BYTEOP2P Dreg_pair Dreg_pair RNDH round into...

Page 665: ...s four bytes together The instruc tion loads the results as bytes on half word boundaries in one 32 bit destination register Some syntax options load the upper byte in the half word and others load th...

Page 666: ...Quad 8 Bit Average Half Word instruction provides byte align ment directly in the source register pairs src_reg_0 typically R1 0 and src_reg_1 typically R3 2 based only on the I0 register The byte ali...

Page 667: ...verage Half Word Option Description RND Rounds up the arithmetic mean T Truncates the arithmetic mean L Loads the results into the lower byte of each destination half word H Loads the results into the...

Page 668: ...thmetic operation is plus for addition The single destination register indicates that averaging is performed Flags Affected None L The ADSP BF535 processor has fewer ASTAT flags and some flags operate...

Page 669: ...uctions on page 20 1 Example r3 byteop2p r1 0 r3 2 rndl r3 byteop2p r1 0 r3 2 rndh r3 byteop2p r1 0 r3 2 tl r3 byteop2p r1 0 r3 2 th r3 byteop2p r1 0 r3 2 rndl r r3 byteop2p r1 0 r3 2 rndh r r3 byteop...

Page 670: ...h Functional Description The Quad 8 Bit Pack instruction packs four 8 bit values half word aligned contained in two source registers into one register byte aligned as shown in Table 18 22 and Table 18...

Page 671: ...more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructio...

Page 672: ...reg pair Dreg pair R b Syntax Terminology Dreg R7 0 Dreg_pair R1 0 R3 2 only Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Quad 8 Bit Subtr...

Page 673: ...hip between the I register bits and the byte alignment is illustrated shown in Table 18 26 In the default source order case for example not the R syntax assume a source register pair contains the data...

Page 674: ...ir The R option causes the low order bytes to come from the high register In the optional reverse source order case for example using the R syn tax the only difference is the source registers swap pla...

Page 675: ...he ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Iss...

Page 676: ...ion Length In the syntax comment b identifies 32 bit instruction length Functional Description The Quad 8 Bit Subtract Absolute Accumulate instruction subtracts four pairs of values takes the absolute...

Page 677: ...g_0 and src_reg_1 based on index registers I0 and I1 The two LSBs of the I0 register determine the byte alignment for source register pair src_reg_0 typically R1 0 The two LSBs of the I1 register dete...

Page 678: ...the forward and reverse byte order ver sions of this instruction By default the low order bytes come from the low register in the register pair The R option causes the low order bytes to come from th...

Page 679: ...ued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instructions on page 20 1 Example saa r1 0 r3 2 r0 i0 r2 i1 parallel fill instructions saa r1 0 r3 2 R r1 i0 r3...

Page 680: ...amming Reference Also See DISALGNEXCPT Load Data Register Special Applications Use the Quad 8 Bit Subtract Absolute Accumulate instruction for block based video motion estimation algorithms using bloc...

Page 681: ...s 32 bit instruction length Functional Description The Quad 8 Bit Unpack instruction copies four contiguous bytes from a pair of source registers adjusting for byte alignment The instruction loads the...

Page 682: ...high register In the optional reverse source order case for example using the R syn tax the only difference is the source registers swap places in their byte ordering Assume the source register pair c...

Page 683: ...BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Require...

Page 684: ...6 r5 byteunpack r1 0 non reversing sources Assuming register I0 s two LSBs 00b R1 0xFEED FACE R0 0xBEEF BADD then this instruction returns R6 0x00BE 00EF R5 0x00BA 00DD Assuming register I0 s two LSBs...

Page 685: ...ng register I0 s two LSBs 10b R1 0xFEED FACE R0 0xBEEF BADD then this instruction returns R6 0x00FA 00CE R5 0x00BE 00EF Assuming register I0 s two LSBs 11b R1 0xFEED FACE R0 0xBEEF BADD then this inst...

Page 686: ...FACE R0 0xBEEF BADD then this instruction returns R6 0x00FE 00ED R5 0x00FA 00CE Assuming register I0 s two LSBs 01b R1 0xFEED FACE R0 0xBEEF BADD then this instruction returns R6 0x00DD 00FE R5 0x00ED...

Page 687: ...Programming Reference 18 47 Video Pixel Operations Assuming register I0 s two LSBs 11b R1 0xFEED FACE R0 0xBEEF BADD then this instruction returns R6 0x00EF 00BA R5 0x00DD 00FE Also See BYTEPACK Quad...

Page 688: ...Instruction Overview 18 48 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 689: ...Vector ABS on page 19 15 Vector Add Subtract on page 19 18 Vector Arithmetic Shift on page 19 23 Vector Logical Shift on page 19 28 Vector MAX on page 19 32 Vector MIN on page 19 35 Vector Multiply on...

Page 690: ...This chapter discusses the instructions that control vector operations Users can take advantage of these instructions to perform simultaneous operations on multiple 16 bit values including add subtrac...

Page 691: ...hi Dreg_hi SIGN Dreg_lo Dreg_lo b Register Consistency The destination registers dest_hi and dest_lo must be halves of the same data register Similarly src0_hi and src0_lo must be halves of the same r...

Page 692: ...e same data registers The results of this step obey the signed multiplication rules sum marized in Table 19 1 Y is the number in src0 and Z is the number in src1 The numbers in src0 and src1 may be po...

Page 693: ...e ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issu...

Page 694: ...6x Blackfin Processor Programming Reference Example r7 h r7 l sign r2 h r3 h sign r2 l r3 l If R2 H 2 R3 H 23 R2 L 2001 R3 L 1234 then R7 H 1257 or 1234 23 R7 L 1257 If R2 H 2 R3 H 23 R2 L 2001 R3 L 1...

Page 695: ...ns If R2 H 2 R3 H 23 R2 L 2001 R3 L 1234 then R7 H 1211 or 1234 23 R7 L 1211 If R2 H 2 R3 H 23 R2 L 2001 R3 L 1234 then R7 H 1257 or 1234 23 R7 L 1257 Also See None Special Applications Use the Sum on...

Page 696: ...reg ASL dest_reg_lo VIT_MAX src_reg ASR Syntax Dual 16 Bit Operation Dreg VIT_MAX Dreg Dreg ASL shift history bits left b Dreg VIT_MAX Dreg Dreg ASR shift history bits right b Single 16 Bit Operation...

Page 697: ...Whereas the dual versions compare four operands to return two maxima the single ver sions compare only two operands to return one maximum The Accumulator extension bits bits 39 32 must be cleared befo...

Page 698: ...Table 19 9 Table 19 6 ASL Version Shifts A0 X A0 W A0 00000000 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXBB Table 19 7 Where BB Indicates 00 z0 and y0 are maxima 01 z0 and y1 are maxima 10 z1 and y0 are maxima 11...

Page 699: ...shown in Table 19 10 the des tination register receives the data shown in Table 19 11 The ASL version shifts A0 left one bit position and appends an LSB to indicate the source of the maximum Converse...

Page 700: ...L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A...

Page 701: ...3 r2 asl shift left dual operation Assume R3 0xFFFF 0000 R2 0x0000 FFFF A0 0x00 0000 0000 This example produces R5 0x0000 0000 A0 0x00 0000 0002 r7 vit_max r1 r0 asr shift right dual operation Assume...

Page 702: ...A0 0x00 0000 0000 r3 l vit_max r1 asr shift right single operation Assume R1 0x1234 FADE A0 0x00 FFFF FFFF This example produces R3 L 0x1234 A0 0x00 7FFF FFFF Also See MAX Special Applications The Co...

Page 703: ...ndividual absolute values of the upper and lower halves of a single 32 bit data register The results are placed into a 32 bit dest_reg using the following rules If the input value is positive or zero...

Page 704: ...VS is set if V is set unaffected otherwise All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products F...

Page 705: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 19 17 Vector Operations Example If r1 0xFFFF 7FFF then r3 abs r1 v produces 0x0001 7FFF Also See ABS Special Applications None...

Page 706: ...0 src_reg_1 dest_0 A1 A0 dest_1 A1 A0 dest_0 A0 A1 dest_1 A0 A1 Syntax Dual 16 Bit Operations Dreg Dreg Dreg opt_mode_0 add add b Dreg Dreg Dreg opt_mode_0 subtract add b Dreg Dreg Dreg opt_mode_0 add...

Page 707: ...ub tract Accumulators subtract A1 from A0 b Syntax Terminology Dreg R7 0 opt_mode_0 optional S CO or SCO opt_mode_1 optional S opt_mode_2 optional ASR or ASL Instruction Length In the syntax comment b...

Page 708: ...ation regis ter SCO Saturate and cross option Combination of S and CO options opt_mode_1 S Saturate the results at 16 or 32 bits depending on the operand size opt_mode_2 ASR Arithmetic shift right Hal...

Page 709: ...d if no carry unaffected if a quad operation V is set if any results overflow cleared if none overflows VS is set if V is set unaffected otherwise All other flags are unaffected L The ADSP BF535 proce...

Page 710: ...ace before storing into destination register r5 r3 r4 r7 r3 r4 asl quad 16 bit operations add subtract subtract add with all results multiplied by 2 left shifted 1 place before storing into destinatio...

Page 711: ...n b Registered Shift Magnitude Dreg ASHIFT Dreg BY Dreg_lo V arithmetic shift b Dreg ASHIFT Dreg BY Dreg_lo V S arithmetic shift with saturation b Arithmetic Left Shift Immediate There is no syntax sp...

Page 712: ...rs Only arithmetic right shifts are supported Left shifts are performed as logical left shifts that may not preserve the sign of the original number In the default case without the optional saturation...

Page 713: ...sence the magnitude is the power of 2 multiplied by the src_reg number Positive magnitudes cause multiplication N x 2n whereas neg ative magnitudes produce division N x 2 n or N 2n The dest_reg and sr...

Page 714: ...overflows cleared if neither overflows VS is set if V is set unaffected otherwise All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently tha...

Page 715: ...sult is r4 0xF000 0001 r4 r5 3 v s same as above but saturate the result r2 ashift r7 by r5 l v arithmetic shift right or left depending on sign of r5 l R7 H and R7 L by magnitude of R5 L r2 ashift r7...

Page 716: ...imm4 V logical shift left immediate b Registered Shift Magnitude Dreg LSHIFT Dreg BY Dreg_lo V logical shift b Syntax Terminology Dreg R7 0 Dreg_lo R7 0 L uimm4 unsigned 4 bit field with a range of 0...

Page 717: ...in shift_magnitude and the result is stored into dest_reg For the LSHIFT versions the sign of the shift magnitude determines the direction of the shift Positive shift magnitudes produce left shifts Ne...

Page 718: ...both are non negative V is cleared All other flags are unaffected L The ADSP BF535 processor has fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more...

Page 719: ...ght shift immediate R5 H and R5 L by 3 bits r4 r5 3 v logical left shift immediate R5 H and R5 L by 3 bits r2 lshift r7 by r5 l v logically shift right or left depending on sign of r5 l R7 H and R7 L...

Page 720: ...positive value nearest to 0x7FFF of the 16 bit half word source registers to the dest_reg The instruction compares the upper half words of src_reg_0 and src_reg_1 and returns that maximum to the upper...

Page 721: ...fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Superviso...

Page 722: ...Instruction Overview 19 34 ADSP BF53x BF56x Blackfin Processor Programming Reference Also See Vector SEARCH Vector MIN MAX MIN Special Applications None...

Page 723: ...lue or the value closest to 0x8000 of the 16 bit half word source registers to the dest_reg This instruction compares the upper half words of src_reg_0 and src_reg_1 and returns that minimum to the up...

Page 724: ...s fewer ASTAT flags and some flags operate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervi...

Page 725: ...ADSP BF53x BF56x Blackfin Processor Programming Reference 19 37 Vector Operations Also See Vector SEARCH Vector MAX MAX MIN Special Applications None...

Page 726: ...perands instruction under the following conditions Both scalar instructions must share the same mode option for example default IS IU T Exception the MAC1 instruction can optionally employ the mixed m...

Page 727: ...Affected This instruction affects the following flags V is set if any result saturates cleared if none saturates VS is set if V is set unaffected otherwise All other flags are unaffected L The ADSP B...

Page 728: ...perform signed integer multiplication r3 h r0 h r1 h r3 l r0 l r1 l s2rnd MAC1 and MAC0 multiply signed fractions Both scale the result on the way to the destination register r0 l r7 l r6 l r0 h r7 h...

Page 729: ...ously and saves the results as a vector couplet See the Arithmetic Operations sections listed above for the scalar instruc tion details Any MAC0 scalar instruction from the list above can be combined...

Page 730: ...s are R7 6 R5 4 R3 2 and R1 0 Syntax Separate the two compatible scalar instructions with a comma to produce a vector instruction Add a semicolon to the end of the combined instruc tion as usual The o...

Page 731: ...r3 h a0 r2 h r3 h both multiply signed fractions into separate Accumulators a0 r1 l r0 l a1 r1 h r0 h same as above but sum result into A1 MAC order is arbitrary a1 r3 h r3 l a0 r3 h r3 h sum product...

Page 732: ...ctions r5 h a1 r3 h r2 h m r5 l a0 r3 l r2 l fu MAC1 multiplies signed fraction by unsigned fraction MAC0 multiplies two unsigned fractions r0 h a1 r3 h r2 h r0 l a0 r3 l r2 l is both MACs perform sig...

Page 733: ...a0 r3 l r7 l fu MAC1 multi plies signed fraction by unsigned fraction MAC0 multiplies two unsigned fractions r1 a1 r3 h r2 h r0 a0 r3 l r2 l is both MACs per form signed integer multiplication r5 a1...

Page 734: ...e instruction returns the same magnitude with the opposite arithmetic sign saturated for each 16 bit half word in the source The instruction calculates by subtracting the source from zero See Saturati...

Page 735: ...ate differently than subsequent Blackfin family products For more information on the ADSP BF535 status flags see Table A 1 on page A 3 Required Mode User Supervisor Parallel Issue This instruction can...

Page 736: ...H Instruction Length In the syntax comment b identifies 32 bit instruction length Functional Description The Vector Pack instruction packs two 16 bit half word numbers into the halves of a 32 bit dat...

Page 737: ...3 Required Mode User Supervisor Parallel Issue This instruction can be issued in parallel with specific other 16 bit instructions For details see Issuing Parallel Instructions on page 20 1 Example r3...

Page 738: ...of 16 bit packed data Two values are tested at a time The Vector Search instruction compares two 16 bit signed half words to values stored in the Accumulators Then it conditionally updates each Accumu...

Page 739: ...r supported compare modes are specified by the mandatory searchmode flag Summary Assumed Pointer P0 src_reg_hi Compared to least significant 16 bits of A1 If com pare condition is met overwrites lower...

Page 740: ...ssued in parallel with the combination of one 16 bit length load instruction to the P0 register and one 16 bit NOP No other instructions can be issued in parallel with the Vector Search instruc tion N...

Page 741: ...e value of P0 corresponding to the value in A1 R0 contains the value of P0 corresponding to the value in A0 Next compare A1 and A0 together and R1 and R0 together to find the single last minimum in th...

Page 742: ...Instruction Overview 19 54 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 743: ...it up to three instructions to be issued in parallel with some limitations A multi issue instruction is 64 bits in length and consists of one 32 bit instruction and two 16 bit instructions All three i...

Page 744: ...bit instruction with a 16 bit NOP automatically inserted into the unused 16 bit slot A 32 bit ALU MAC instruction A 16 bit instruction Alternately it is also possible to issue two 16 bit instructions...

Page 745: ...thmetic Operations ABS Absolute Value Add Only the versions that support optional saturation Add Subtract Prescale Up Add Subtract Prescale Down EXPADJ Exponent Detection MAX Maximum MIN Minimum Modif...

Page 746: ...opulation Count Logical Operations Exclusive OR Bit Wise XOR Move Move Register 40 bit Accumulator versions only Move Register Half Shift Rotate Operations Arithmetic Shift Saturating and Accumulator...

Page 747: ...ultiply and Multiply Accumulate to Half Register Multiply and Multiply Accumulate to Data Register Vector ABS Vector Absolute Value Vector Add Subtract Vector Arithmetic Shift Vector Logical Shift Vec...

Page 748: ...are memory access instructions then both cannot use P registers as address registers In this case at least one memory access instruction must be an I register version Video Pixel Operations ALIGN8 AL...

Page 749: ...crement Ireg versions only Modify Increment Ireg versions only Subtract Immediate Ireg versions only Load Store Load Pointer Register Load Data Register Load Half Word Zero Extended Load Half Word Sig...

Page 750: ...een the data in R1 and R3 then the data in R0 and R2 saa r1 0 r3 2 r0 i0 r2 i1 saa r1 0 r3 2 r r1 i0 r3 i1 mnop r1 i0 r3 i1 Table 20 4 Group2 Compatible 16 Bit Instructions Instruction Name Notes Load...

Page 751: ...mulate to Accumulator while loading a data register and storing a data register using an Ireg pointer A1 R2 L R1 L A0 R2 H R1 H R2 H W I2 I3 R3 Multiply and accumulate while loading two data registers...

Page 752: ...Examples 20 10 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 753: ...nstruction bus and the data bus the Watchpoint Unit provides several mechanisms for examining program behavior After counting the number of times a particular address is matched the unit schedules an...

Page 754: ...ruction Watchpoint Address Control register WPIACTL Two Data Watchpoint Address registers WPDA 1 0 Two Data Watchpoint Address Count registers WPDACNT 1 0 The Data Watchpoint Address Control register...

Page 755: ...ped together into one data address range watchpoint WPDA 1 0 The instruction and data count value registers must be loaded with the number of times the watchpoint must match minus one After the count...

Page 756: ...e associated to form a range two additional bits are used as shown in Table 21 3 Table 21 2 WPIACTL Control Bits Bit Name Description EMUSWx Determines whether an instruction address match causes eith...

Page 757: ...etermine which watchpoint trig gered the exception Next the code writes the start address of the new code in the RETX register and then returns from the exception to the new code Because the exception...

Page 758: ...2 The WPIACNTn register will decrement to 0x0000 when the programmed count expires Figure 21 1 Instruction Watchpoint Address Registers Table 21 4 Instruction Watchpoint Register Memory mapped Address...

Page 759: ...ster have no effect unless the WPPWR bit is set Figure 21 2 Instruction Watchpoint Address Count Registers Table 21 5 Instruction Watchpoint Address Count Register Memory mapped Addresses Register Nam...

Page 760: ...uction address watchpoint WPIA4 WPIAEN5 Valid when WPIREN45 0 0 Disable instruction address watchpoint WPIA5 1 Enable instruction address watchpoint WPIA5 WPAND 0 Any enabled watchpoint triggers an ex...

Page 761: ...n event 1 Match on WPIA1 causes an emulation event WPIREN23 0 Disable range comparison 1 Enable range comparison Start address WPIA2 End address WPIA3 WPIRINV23 WPIAEN2 Valid when WPIREN23 0 0 Disable...

Page 762: ...s Corresponding count values in the Data Watchpoint Address Count regis ters WPDACNTn are decremented on each match Table 21 6 Data Address Watchpoints Bit Name Description WPDACCn Determines whether...

Page 763: ...ess bus matches a value in the WPDAn reg isters Load this WPDACNTn register with a value that is one less than the number of times the watchpoint must match before triggering an event Figure 21 5 Data...

Page 764: ...formation about the bits in the Data Watchpoint Address Control register WPDACTL see Data Address Watchpoints on page 21 10 Figure 21 6 Data Watchpoint Address Count Value Registers 31 30 29 28 27 26...

Page 765: ...ses on WPDA0 or on the WPDA0 to WPDA1 range WPDACC0 1 0 WPDREN01 0 Disable range comparison 1 Enable range comparison Start address WPDA0 End address WPDA1 WPDRINV01 0 Inclusive range comparison insid...

Page 766: ...4 3 2 1 0 X X X X X X 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X X X X X X X X X X X X X X X X Watchpoint Status Register WPSTAT STATIA0 0 Neither WPIA0 nor the WPIA0 to WPIA1 ran...

Page 767: ...n a zero overhead loop the iteration count is available in the Loop Count registers LC0 and LC1 The trace buffer can be configured to omit the recording of changes in program flow that match either th...

Page 768: ...it is rec ommended that TBUF be read in a non interruptible section of code Note if single level compression has occurred the least significant bit LSB of the branch target address is set If two level...

Page 769: ...ce Buffer Control Register TBUFCTL TBUFPWR 0 Trace buffer is off 1 Trace buffer is active TBUFEN 0 Trace buffer disabled 1 Trace buffer enabled TBUFOVF 0 Overflows are ignored 1 Trace buffer overflow...

Page 770: ...program flow discontinuities may be read from TBUF and stored in memory by the code shown in Listing 21 1 L While TBUF is being read be sure to disable the trace buffer from recording new discontinuit...

Page 771: ...art loop1_end lc0 p5 loop1_start r7 p3 read from TBUF loop1_end p4 r7 write to memory and increment p2 p4 pointer to the next available buf location is saved in the header of buf r7 7 p5 3 sp restore...

Page 772: ...Monitor Control register PFCTL shown in Figure 21 13 Once the unit is enabled individual count enable bits PFCENn take effect Use the PFCENx bits to enable or disable the performance monitors in User...

Page 773: ...0 causes emulation event PFCEN0 1 0 00 Disable Performance Monitor 0 01 Enable Performance Monitor 0 in User mode only 10 Enable Performance Monitor 0 in Supervisor mode only 11 Enable Performance Mon...

Page 774: ...NC SSYNC 0x0B EXCPT instructions 0x0C CSYNC SSYNC instructions 0x0D Committed instructions 0x0E Interrupts taken 0x0F Misaligned address violation exceptions 0x10 Stall cycles due to read after write...

Page 775: ...tran sition 0x94 Data memory store buffer forward stalls due to lack of committed data from processor 0x95 Data memory fill buffer stalls 0x96 Data memory array or TAG collision stalls DAG to DAG or D...

Page 776: ...n another read from CYCLES In User mode these two registers may be read but not written In Super visor and Emulator modes they are read write registers To enable the cycle counters set the CCEN bit in...

Page 777: ...L The CYCLES and CYCLES2 registers are not system MMRs but are instead system registers Figure 21 14 Execution Cycle Count Registers X X X X X X X X X X X X X X X X 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 778: ...ystem Configuration Register SYSCFG SNEN Self Nesting Interrupt Enable SSSTEP Supervisor Sin gle Step When set a Supervisor exception is taken after each instruction is executed It applies only to Use...

Page 779: ...egister The DSP Device ID register DSPID shown in Figure 21 16 is a read only register and is part of the core Figure 21 16 DSP Device ID Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 1 1...

Page 780: ...Product Identification Register 21 28 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 781: ...ral of the descriptions do not apply to the ADSP BF535 processor These are In Table 3 3 on page 3 4 IDLE is also a protected instruction and is not accessible in User mode In Idle State on page 3 9 an...

Page 782: ...ag is SET OR CLEARED depending on exe cution of the instruction indicates that the flag is CLEARED by execution of the instruction U indicates that the flag state is UNDEFINED following execution of t...

Page 783: ...ed Load Byte Sign Extended Store Pointer Register Store Data Register Store High Data Register Half Store Low Data Register Half Store Byte Move Register except acc to dreg indicates that the flag is...

Page 784: ...ointer Compare Accumulator U Move CC Negate CC AND NOT One s Complement Table A 1 ASTAT Flag Behavior for the ADSP BF535 Cont d Instruction CC AZ AN AC0_ COPY V_ COPY AQ indicates that the flag is NOT...

Page 785: ...U Logical Shift to dreg U Logical Shift to A0 U U Table A 1 ASTAT Flag Behavior for the ADSP BF535 Cont d Instruction CC AZ AN AC0_ COPY V_ COPY AQ indicates that the flag is NOT AFFECTED by executio...

Page 786: ...o preg or ireg Modify Increment extracted to dreg Modify Increment to acc U U U U Table A 1 ASTAT Flag Behavior for the ADSP BF535 Cont d Instruction CC AZ AN AC0_ COPY V_ COPY AQ indicates that the f...

Page 787: ...le Core Synchronize System Synchronize EMUEXCPT Force Emulation Disable Interrupts Enable Interrupts RAISE Force Interrupt Reset Table A 1 ASTAT Flag Behavior for the ADSP BF535 Cont d Instruction CC...

Page 788: ...8 Bit Subtract Absolute Accumulate U U U U BYTEUNPACK Quad 8 Bit Unpack U U U U Add on Sign U U U U VIT_MAX Compare Select U U Table A 1 ASTAT Flag Behavior for the ADSP BF535 Cont d Instruction CC AZ...

Page 789: ...ag Behavior for the ADSP BF535 Cont d Instruction CC AZ AN AC0_ COPY V_ COPY AQ indicates that the flag is NOT AFFECTED by execution of the instruction indicates that the flag is SET OR CLEARED depend...

Page 790: ...ADSP BF535 Flags A 10 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 791: ...ewing the PDF version of this document click a refer ence in the See Section column to jump to additional information about the MMR L1 Data Memory Controller Registers L1 Data Memory Controller regist...

Page 792: ...11 DCPLB_ADDRx Registers on page 6 59 0xFFE0 0130 DCPLB_ADDR12 DCPLB_ADDRx Registers on page 6 59 0xFFE0 0134 DCPLB_ADDR13 DCPLB_ADDRx Registers on page 6 59 0xFFE0 0138 DCPLB_ADDR14 DCPLB_ADDRx Regis...

Page 793: ...LB_DATAx Registers on page 6 57 0xFFE0 0234 DCPLB_DATA13 DCPLB_DATAx Registers on page 6 57 0xFFE0 0238 DCPLB_DATA14 DCPLB_DATAx Registers on page 6 57 0xFFE0 023C DCPLB_DATA15 DCPLB_DATAx Registers o...

Page 794: ...CPLB_ADDR0 ICPLB_ADDRx Registers on page 6 60 0xFFE0 1104 ICPLB_ADDR1 ICPLB_ADDRx Registers on page 6 60 0xFFE0 1108 ICPLB_ADDR2 ICPLB_ADDRx Registers on page 6 60 0xFFE0 110C ICPLB_ADDR3 ICPLB_ADDRx...

Page 795: ...TAx Registers on page 6 55 0xFFE0 121C ICPLB_DATA7 ICPLB_DATAx Registers on page 6 55 0xFFE0 1220 ICPLB_DATA8 ICPLB_DATAx Registers on page 6 55 0xFFE0 1224 ICPLB_DATA9 ICPLB_DATAx Registers on page 6...

Page 796: ...Vector Table on page 4 42 0xFFE0 200C EVT3 EVX Core Event Vector Table on page 4 42 0xFFE0 2010 EVT4 Core Event Vector Table on page 4 42 0xFFE0 2014 EVT5 IVHW Core Event Vector Table on page 4 42 0x...

Page 797: ...2 0xFFE0 203C EVT15 IVG15 Core Event Vector Table on page 4 42 0xFFE0 2104 IMASK IMASK Register on page 4 38 0xFFE0 2108 IPEND IPEND Register on page 4 40 0xFFE0 210C ILAT ILAT Register on page 4 39 0...

Page 798: ...FE0 6100 TBUF TBUF Register on page 21 18 Table B 6 Watchpoint and Patch Registers Memory mapped Address Register Name See Section 0xFFE0 7000 WPIACTL WPIACTL Register on page 21 7 0xFFE0 7040 WPIA0 W...

Page 799: ...0 7140 WPDA0 WPDAn Registers on page 21 10 0xFFE0 7144 WPDA1 WPDAn Registers on page 21 10 0xFFE0 7180 WPDACNT0 WPDACNTn Registers on page 21 11 0xFFE0 7184 WPDACNT1 WPDACNTn Registers on page 21 11 0...

Page 800: ...Performance Monitor Registers B 10 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 801: ...sent or recognize bit fields within the opcodes This more explicit format expands the listings to more pages but is easier and quicker to reference The success of this document is measured by how lit...

Page 802: ...isters can be accessed as 32 bit registers or optionally as two independent 16 bit registers The least significant 16 bits of each register is called the low half and is designated with L following th...

Page 803: ...at normally contain the base address in bytes of the circular buffer Abbreviated as Breg Table C 2 Processor Sections Processor Description Data Address Generator DAG Calculates the effective address...

Page 804: ...3 2 The larger number must is written first Note The hardware supports only odd even pairs for example R7 6 R5 4 R3 2 and R1 0 Some instructions require a group of adjacent registers Adjacent reg iste...

Page 805: ...R3 R2 R1 and R0 are abbreviated R3 0 This nomen clature is similar to that used for valid Data Register pairs but here more than a single pair can be represented Another example is the least significa...

Page 806: ...ppcrel with the following modifiers the decimal number indicates how many bits the value can include for example lppcrel5 is a 5 bit value any alignment requirements are designated by an optional m su...

Page 807: ...ulator 0 Sticky Overflow set when AV0 is set but remains set until explicitly cleared by user code AV1 Accumulator 1 Overflow AVS1 Accumulator 1 Sticky Overflow set when AV1 is set but remains set unt...

Page 808: ...Opcode Range col umn Instructions that support variable arguments such as a choice of source or destination registers optional modes or constants span a range of hex values The minimum and maximum al...

Page 809: ...Opcode Representation Instruction and Version Bin Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Instruction Name Single Hex Value bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit S...

Page 810: ...the range of operation codes shown for some instructions For example one version of the Zero Overhead Loop Setup instruction spans the opcode range E080 0000 through E08F 03FF as shown in the excerpt...

Page 811: ...gher address The reason is that the instruction length is encoded in the most significant 16 bits of the opcode By storing this information in the lower addresses the Program Sequencer can determine i...

Page 812: ...his byte sequence is displayed in ascending address order as 0xED 0xFE 0xCE 0xFA or in 16 bit format as 0xEDFE 0xCEFA Or in 32 bit format as 0xFEED FACE This reference appendix lists the opcodes in th...

Page 813: ...pcrel13m2 divided by 2 JUMP S pcrel13m2 Jump 0xE200 0000 0xE2FF FFFF 1 1 1 0 0 0 1 0 Most significant bits of pcrel25m2 Least significant bits of pcrel25m2 divided by 2 JUMP L pcrel25m2 Conditional J...

Page 814: ...080 0000 0xE08F 03FF 1 1 1 0 0 0 0 0 1 0 0 0 pcrel5m2 divided by 2 0 0 0 0 x x pcrel11m2 divided by 2 LOOP loop_name LC0 LOOP_BEGIN loop_name LOOP_END loop_name is mapped to LSETUP pcrel5m2 pcrel11m2...

Page 815: ...determines pcrel5m2 and the address of LOOP_END determines pcrel11m2 Zero Overhead Loop Setup 0xE0B0 0000 0xE0BF F3FF 1 1 1 0 0 0 0 0 1 0 1 1 pcrel5m2 divided by 2 Preg x x pcrel11m2 divided by 2 LOO...

Page 816: ...FFF 1 1 1 0 0 0 0 1 0 1 0 Reg grp Reg uimm16 reg_hi uimm16 Load Immediate 0xE180 0000 0xE19F FFFF 1 1 1 0 0 0 0 1 1 0 0 Reg grp Reg uimm16 reg uimm16 Z Load Immediate 0xC408 003F 1 1 0 0 0 1 0 x x x 0...

Page 817: ...r Register 0xAC00 0xAFFF 1 0 1 0 1 1 uimm6m4 divided by 4 Source Preg Dest Preg Preg Preg uimm6m4 Load Pointer Register 0xE500 0000 0xE53F 7FFF 1 1 1 0 0 1 0 1 0 0 Source Preg Dest Preg uimm17m4 divid...

Page 818: ...43F FFFF 1 1 1 0 0 1 0 0 0 0 Preg Dreg uimm17m4 divided by 4 Dreg Preg uimm17m4 Load Data Register 0x8000 0x81FF 1 0 0 0 0 0 0 Dest Dreg Index Preg Pointer Preg Dreg Preg Preg NOTE Pointer Preg number...

Page 819: ...ro Extended 0xA400 0xA7FF 1 0 1 0 0 1 uimm5m2 divided by 2 Preg Dreg Dreg W Preg uimm5m2 Z Load Half Word Zero Extended 0xE440 0000 0xE47F 8FFF 1 1 1 0 0 1 0 0 0 1 Preg Dreg uimm16m2 divided by 2 Dreg...

Page 820: ...eg Dreg uimm16m2 divided by 2 Dreg W Preg uimm16m2 X Load Half Word Sign Extended 0xE540 8000 0xE57F FFFF 1 1 1 0 0 1 0 1 0 1 Preg Dreg uimm16m2 divided by 2 Dreg W Preg uimm16m2 X Load Half Word Sign...

Page 821: ...Low Data Register Half 0x9D20 0x9D3F 1 0 0 1 1 1 0 1 0 0 1 Ireg Dreg Dreg_lo W Ireg Load Low Data Register Half 0x9C20 0x9C3F 1 0 0 1 1 1 0 0 0 0 1 Ireg Dreg Dreg_lo W Ireg Load Low Data Register Hal...

Page 822: ...imm15 Dreg B Preg uimm15 Z Load Byte Zero Extended 0xE480 8000 0xE4BF FFFF 1 1 1 0 0 1 0 0 1 0 Preg Dreg uimm15 Dreg B Preg uimm15 Z Load Byte Sign Extended 0x9940 0x997F 1 0 0 1 1 0 0 1 0 1 Preg Dreg...

Page 823: ...ster 0x92C0 0x92FF 1 0 0 1 0 0 1 0 1 1 Dest Pointer Preg Source Preg Preg Preg Store Pointer Register 0xBC00 0xBFFF 1 0 1 1 1 1 uimm6m4 divided by 4 Source Pointer Preg Dest Preg Preg uimm6m4 Preg Sto...

Page 824: ...6m4 Dreg Store Data Register 0xE600 0000 0xE63F 7FFF 1 1 1 0 0 1 1 0 0 0 Preg Dreg uimm17m4 divided by 4 Preg uimm17m4 Dreg Store Data Register 0xE600 8000 0xE63F FFFF 1 1 1 0 0 1 1 0 0 0 Preg Dreg ui...

Page 825: ...1 0 Ireg Dreg W Ireg Dreg_hi Store High Data Register Half 9EC0 0x9EDF 1 0 0 1 1 1 1 0 1 1 0 Ireg Dreg W Ireg Dreg_hi Store High Data Register Half 0x8C00 0x8DFF 1 0 0 0 1 1 0 Source Dreg Pointer Pre...

Page 826: ...the same Preg number Otherwise this opcode represents a post modify version of this instruction Store Low Data Register Half 0x9700 0x973F 1 0 0 1 0 1 1 1 0 0 Preg Dreg W Preg Dreg Store Low Data Regi...

Page 827: ...ber If so this opcode represents a non post modify instruction version Store Byte 0x9B00 0x9B3F 1 0 0 1 1 0 1 1 0 0 Preg Dreg B Preg Dreg Store Byte 0x9A00 0x9A3F 1 0 0 1 1 0 1 0 0 0 Preg Dreg B Preg...

Page 828: ...eg genreg dagreg dagreg genreg USP USP genreg Dreg sysreg sysreg Dreg sysreg Preg sysreg USP Move Register 0xC408 C000 0xC408 C038 1 1 0 0 0 1 0 x x x 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A0 A1...

Page 829: ...0xC12B 3800 0xC12B 39C0 1 1 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 0 1 1 1 0 0 Dreg_eve n 0 0 0 0 0 0 Dreg_even A0 ISS2 Move Register 0xC00F 1800 0xC00F 19C0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 Dreg_...

Page 830: ...0 0 0 0 0 0 Dreg_even A0 Dreg_odd A1 Dreg_odd A1 Dreg_even A0 Move Register 0xC08F 3800 0xC08F 39C0 1 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 1 0 0 Dreg_eve n of the register pair 0 0 0 0 0 0 Dreg_even...

Page 831: ...63F 0 0 0 0 0 1 1 0 0 0 Dest Dreg Source Dreg IF CC Dreg Dreg Move Conditional 0x0640 0x067F 0 0 0 0 0 1 1 0 0 1 Dest Dreg Source Preg IF CC Dreg Preg Move Conditional 0x0680 0x06BF 0 0 0 0 0 1 1 0 1...

Page 832: ...0 0 0 1 0 x x x 0 0 1 0 1 0 0 0 0 0 Dest Dreg 0 0 0 1 1 1 1 1 1 Dreg_lo A0 X Move Register Half 0xC40A 4000 0xC40A 4E00 1 1 0 0 0 1 0 x x x 0 0 1 0 1 0 0 1 0 0 Dest Dreg 0 0 0 1 1 1 1 1 1 Dreg_lo A1...

Page 833: ...Dreg 0 0 0 0 0 0 Dreg_lo A0 Move Register Half 0xC083 3800 0xC083 39C0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 Dreg 0 0 0 0 0 0 Dreg_lo A0 FU Move Register Half 0xC103 3800 0xC103 39C0 1 1 0 0 0...

Page 834: ...0 0 0 0 0 Dreg_lo A0 IH Move Register Half 0xC007 1800 0xC007 19C0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 0 Dreg 0 0 0 0 0 0 Dreg_hi A1 Move Register Half 0xC107 1800 0xC107 19C0 1 1 0 0 0 0 0 1...

Page 835: ...00 0xC167 19C0 1 1 0 0 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 0 0 Dreg 0 0 0 0 0 0 Dreg_hi A1 IH Move Register Half 0xC007 3800 0xC007 39C0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 Dreg 0 0 0 0 0 0 Dr...

Page 836: ...0 0 Dreg_lo A0 Dreg_hi A1 S2RND Dreg_hi A1 Dreg_lo A0 S2RND Move Register Half 0xC127 3800 0xC127 39C0 1 1 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0 0 Dreg 0 0 0 0 0 0 Dreg_lo A0 Dreg_hi A1 ISS2 Dreg_h...

Page 837: ...register number represents the lowest register in the range to be used Example 100b in that field means R7 through R4 are used SP R7 Dreglim Push Multiple 0x04C0 0x04C5 0 0 0 0 0 1 0 0 1 1 0 0 0 Preg...

Page 838: ...0 1 0 0 1 0 0 0 0 Preg NOTE The embedded register number represents the lowest register in the range to be used Example 010b in that field means P5 through P2 are used The highest useful value allowed...

Page 839: ...C Dreg imm3 Compare Data Register 0x0880 0x08BF 0 0 0 0 1 0 0 0 1 0 Source reg Dest reg CC Dreg Dreg Compare Data Register 0x0C80 0x0CBF 0 0 0 0 1 1 0 0 1 0 imm3 Dest reg CC Dreg imm3 Compare Data Reg...

Page 840: ...er Register 0x0CC0 0x0CFF 0 0 0 0 1 1 0 0 1 1 imm3 Dest reg CC Preg imm3 Compare Pointer Register 0x0940 0x097F 0 0 0 0 1 0 0 1 0 1 Source reg Dest reg CC Preg Preg Compare Pointer Register 0x0D40 0x0...

Page 841: ...C 0x0200 0x0207 0 0 0 0 0 0 1 0 0 0 0 0 0 Dreg Dreg CC Move CC 0x0380 0x039F 0 0 0 0 0 0 1 1 1 0 0 ASTAT bit statbit CC Move CC 0x03A0 0x03BF 0 0 0 0 0 0 1 1 1 0 1 ASTAT bit statbit CC Move CC 0x03C0...

Page 842: ...ASTAT bit CC statbit Move CC 0x0340 035F 0 0 0 0 0 0 1 1 0 1 0 ASTAT bit CC statbit Move CC 0x0360 0x037F 0 0 0 0 0 0 1 1 0 1 1 ASTAT bit CC statbit Negate CC 0x0218 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 CC...

Page 843: ...c 0 Dreg Dreg Dreg Dreg Exclusive OR 0x5800 0x59FF 0 1 0 1 1 0 0 Dest Dreg Src 1 Dreg Src 0 Dreg Dreg Dreg Dreg Bit Wise Exclusive OR 0xC60B 0000 0xC60B 0E38 1 1 0 0 0 1 1 0 0 0 x x 1 0 1 1 0 0 0 0 De...

Page 844: ...uimm5 Dest Dreg BITTGL Dreg uimm5 Bit Test 0x4900 0x49FF 0 1 0 0 1 0 0 1 uimm5 Dest Dreg CC BITTST Dreg uimm5 Bit Test 0x4800 0x48FF 0 1 0 0 1 0 0 0 uimm5 Dest Dreg CC BITTST Dreg uimm5 Bit Field Dep...

Page 845: ...0 1 0 0 0 0 0 0 0 0 0 0 x x x Source 0 Dreg Source 1 Dreg BITMUX Dreg Dreg A0 ASR Bit Multiplex 0xC608 4000 0xC608 403F 1 1 0 0 0 1 1 0 0 x x 0 1 0 0 0 0 1 0 0 0 0 0 x x x Source 0 Dreg Source 1 Dreg...

Page 846: ...0 0 0 0 0 1 0 0 Source Dreg Dest Dreg Dreg Dreg Dreg 1 Add with Shift 0x4140 0x417F 0 1 0 0 0 0 0 1 0 1 Source Dreg Dest Dreg Dreg Dreg Dreg 2 Shift with Add 0x5C00 0x5DFF 0 1 0 1 1 1 0 Dest Preg Src...

Page 847: ...o uimm4 S Arithmetic Shift 0xC680 5000 0xC680 5E7F 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0 0 1 0 1 Dest Dreg uimm4 Source Dreg Dreg_lo Dreg_hi uimm4 S Arithmetic Shift 0xC680 6000 0xC680 6E7F 1 1 0 0 0 1 1 0...

Page 848: ...reg Arithmetic Shift 0xC600 0000 0xC600 0E3F 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0 0 0 0 0 Dest Dreg x x x Source Dreg sh_mag Dreg Dreg_lo ASHIFT Dreg_lo BY Dreg_lo Arithmetic Shift 0xC600 1000 0xC600 1E3F...

Page 849: ...Dreg_lo S Arithmetic Shift 0xC600 7000 0xC600 7E3F 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0 0 1 1 1 Dest Dreg x x x Source Dreg sh_mag Dreg Dreg_hi ASHIFT Dreg_hi BY Dreg_lo S Arithmetic Shift 0xC602 0000 0xC...

Page 850: ...on NOTE This Preg Preg 1 instruction produces the same opcode as the special case of the Preg Preg Preg Add instruction where both input operands are the same Preg e g p3 p0 p0 that accom plishes the...

Page 851: ...reg Dreg_hi Dreg_hi uimm4 Logical Shift 0xC680 8000 0xC680 8E7F 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 0 1 0 0 0 Dest Dreg uimm4 Source Dreg Dreg_lo Dreg_lo uimm4 Logical Shift 0xC680 9000 0xC680 9E7F 1 1 0 0...

Page 852: ...5 0 0 0 A0 A0 uimm5 Logical Shift 0xC683 4000 0xC683 40F8 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 1 0 1 0 0 0 0 0 uimm5 0 0 0 A0 A0 uimm5 Logical Shift 0xC683 5100 0xC683 51F8 1 1 0 0 0 1 1 0 1 x x 0 0 0 1 1 0...

Page 853: ...Dreg_lo BY Dreg_lo Logical Shift 0xC600 B000 0xC600 BE3F 1 1 0 0 0 1 1 0 0 x x 0 0 0 0 0 1 0 1 1 Dest Dreg x x x Source Dreg sh_mag Dreg Dreg_hi LSHIFT Dreg_hi BY Dreg_lo Logical Shift 0xC602 8000 0xC...

Page 854: ...x 0 0 0 1 1 1 0 0 1 0 0 0 imm6 0 0 0 A1 ROT A1 BY imm6 Rotate 0xC602 C000 0xC602 CE3F 1 1 0 0 0 1 1 0 0 x x 0 0 0 1 0 1 1 0 0 Dest Dreg x x x Source Dreg rot_mag Dreg Dreg ROT Dreg BY Dreg_lo Rotate...

Page 855: ...0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A1 ABS A1 Absolute Value 0xC410 C03F 1 1 0 0 0 1 0 x x x 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A1 ABS A1 A0 ABS A0 Absolute Value 0xC407 8000 0xC407 8E38 1 1 0 0...

Page 856: ...Add 0xC402 4000 0xC402 4E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 1 0 0 1 0 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_lo Dreg_lo Dreg_hi NS Add 0xC402 8000 0xC402 8E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 1 0...

Page 857: ...i NS Add 0xC402 2000 0xC402 2E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 1 0 0 0 1 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_lo Dreg_lo Dreg_lo S Add 0xC402 6000 0xC402 6E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 1...

Page 858: ...2 EE3F 1 1 0 0 0 1 0 x x x 1 0 0 0 1 0 1 1 1 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_hi Dreg_hi Dreg_hi S Add Subtract Prescale Down 0xC405 9000 0xC405 9E3F 1 1 0 0 0 1 0 x x x 0 0 0 1 0 1...

Page 859: ...0 0 0 Source 0 Dreg Source 1 Dreg Dreg_hi Dreg Dreg RND12 Add Subtract Prescale Up 0xC405 4000 0xC405 4E3F 1 1 0 0 0 1 0 x x x 0 0 0 1 0 1 0 1 0 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_lo D...

Page 860: ...8000 0xC607 8E3F 1 1 0 0 0 1 1 0 0 x x 0 0 1 1 1 1 0 0 0 Dest Dreg x x x Source 0 Dreg Source 1 Dreg Dreg_lo EXPADJ Dreg_lo Dreg_lo Exponent Detection 0xC607 C000 0xC607 CE3F 1 1 0 0 0 1 1 0 0 x x 0...

Page 861: ...00 0x443F 0 1 0 0 0 1 0 0 0 0 Source Preg Dest Preg Preg Preg Modify Decrement 0x9E70 0x9E7F 1 0 0 1 1 1 1 0 0 1 1 1 Mreg Ireg Ireg Mreg Modify Increment 0xC40B 803F 1 1 0 0 0 1 0 x x x 0 0 1 0 1 1 1...

Page 862: ...parallel with a Multiply 16 Bit Operands instruction add 0x0800 0000 to the Multiply 16 Bit Operands opcode Dreg_hi A0 A1 Multiply 16 Bit Operands 0xC200 2000 0xC200 27FF 1 1 0 0 0 0 1 0 0 0 0 0 0 0...

Page 863: ...Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_lo Dreg_lo_hi Dreg_lo_hi S2RND Multiply 16 Bit Operands 0xC320 200 0xC320 27FF0 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 Dreg half Dest Dreg src_reg_ 0...

Page 864: ...0 0 Dreg half Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg NOTE When issuing compatible load store instructions in parallel with a Multiply 16 Bit Operands instruction add 0x0800 0000 to the Multiply 16...

Page 865: ...erands 0xC224 0000 0xC224 C1FF 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 Dreg half 0 0 0 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi Dreg_lo_hi Dreg_lo_hi S2RND Multiply 16 Bit Operands 0xC324 0000 0x...

Page 866: ...Bit Operands 0xC254 0000 0xC254 C1FF 1 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 Dreg half 0 0 0 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi Dreg_lo_hi Dreg_lo_hi T M Multiply 16 Bit Operands 0xC2D4 000...

Page 867: ...reg_ 0 Dreg src_reg_ 1 Dreg Dreg_odd Dreg_lo_hi Dreg_lo_hi FU Multiply 16 Bit Operands 0xC30C 0000 0xC30C C1FF 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 Dreg half 0 0 0 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1...

Page 868: ...1 0 0 0 0 1 0 0 0 1 1 1 1 0 0 Dreg half 0 0 0 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_odd Dreg_lo_hi Dreg_lo_hi S2RND M Multiply 16 Bit Operands 0xC33C 0000 0xC33C C1FF 1 1 0 0 0 0 1 1 0 0...

Page 869: ...Multiply and Multiply Accumulate to Accumulator 0xC083 0000 0xC083 063F 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Dreg half 0 0 0 src_reg_ 0 Dreg src_reg_ 1 Dreg A0 Dreg_lo_hi Dreg_lo_hi FU Multiply a...

Page 870: ...0 0 1 Dreg half 0 0 0 src_reg_ 0 Dreg src_reg_ 1 Dreg NOTE When issuing compatible load store instructions in parallel with a Multiply and Multiply Accumu late instruction add 0x0800 0000 to the Mult...

Page 871: ...ate to Accumulator 0xC080 1800 0xC080 D83F 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Dreg half 0 1 1 0 0 0 0 0 src_reg_ 0 Dreg src_reg_ 1 Dreg A1 Dreg_lo_hi Dreg_lo_hi FU Multiply and Multiply Accumulate to Acc...

Page 872: ...y Accumulate to Accumulator 0xC081 1800 0xC081 D83F 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 Dreg half 0 1 1 0 0 0 0 0 src_reg_ 0 Dreg src_reg_ 1 Dreg A1 Dreg_lo_hi Dreg_lo_hi FU Multiply and Multiply Accumula...

Page 873: ...late to Accumulator 0xC082 1800 0xC082 D83F 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 Dreg half 0 1 1 0 0 0 0 0 src_reg_ 0 Dreg src_reg_ 1 Dreg A1 Dreg_lo_hi Dreg_lo_hi FU Multiply and Multiply Accumulate to Ac...

Page 874: ...es the input operand register to the right of the operand NOTE When issuing compatible load store instructions in parallel with a Multiply and Multiply Accumu late instruction add 0x0800 0000 to the M...

Page 875: ...alf Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi S2RND Multiply and Multiply Accumulate to Half Register 0xC123 2000 0xC123 27FF 1 1 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0...

Page 876: ...umulate to Half Register 0xC043 2800 0xC043 2FFF 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 Dreg half Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi T Multiply and Multiply...

Page 877: ...0 Dreg src_reg_ 1 Dreg Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi FU Multiply and Multiply Accumulate to Half Register 0xC103 3000 0xC103 37FF 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 Dreg half Dest Dreg src_r...

Page 878: ...iply and Multiply Accumulate opcode Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi IH Multiply and Multiply Accumulate to Half Register 0xC004 1800 0xC004 D9FF 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Dreg half 0 1 1 0 0 De...

Page 879: ...te to Half Register 0xC124 1800 0xC124 D9FF 1 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi ISS2 Multiply and Multiply Ac...

Page 880: ...1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi TFU M Multiply and Multiply Accumulate to Half Register 0xC034 1800 0xC034 D9FF 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 Dreg...

Page 881: ...to Half Register 0xC185 1800 0xC185 D9FF 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi IU Multiply and Multiply Accumul...

Page 882: ...mulate to Half Register 0xC095 1800 0xC095 D9FF 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi FU M Multiply and Multipl...

Page 883: ...f 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg NOTE When issuing compatible load store instructions in parallel with a Multiply and Multiply Accumu late instruction add 0x0800 0000 to the Multi...

Page 884: ...umulate to Half Register 0xC026 1800 0xC026 D9FF 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi S2RND Multiply and Multi...

Page 885: ...o Half Register 0xC056 1800 0xC056 D9FF 1 1 0 0 0 0 0 0 0 1 0 1 0 1 1 0 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi T M Multiply and Multiply Accumul...

Page 886: ...des the destination Data Register src_reg_0 Dreg encodes the input operand register to the left of the operand src_reg_1 Dreg encodes the input operand register to the right of the operand NOTE When i...

Page 887: ...ply Accumulate opcode Dreg_even A0 Dreg_lo_hi Dreg_lo_hi ISS2 Multiply and Multiply Accumulate to Data Register 0xC00D 0800 0xC00D 0FFF 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 Dreg half Dest Dreg sr...

Page 888: ...Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_even A0 Dreg_lo_hi Dreg_lo_hi FU Multiply and Multiply Accumulate to Data Register 0xC10D 1000 0xC10D 17FF 1 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 0 Dreg hal...

Page 889: ...Data Register 0xC028 1800 0xC028 D9FF 1 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi S2RND Multiply and Multiply Accum...

Page 890: ...and Multiply Accumulate opcode Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi ISS2 M Multiply and Multiply Accumulate to Data Register 0xC009 1800 0xC009 D9FF 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Dreg half 0 1 1 0 0 D...

Page 891: ...0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi IS M Multiply and Multiply Accumulate to Data Register 0xC039 1800 0xC039 D9FF 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 Dreg half 0...

Page 892: ...cumulate to Data Register 0xC12A 1800 0xC12A D9FF 1 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 Dreg half 0 1 1 0 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi ISS2 Multiply and Mult...

Page 893: ...opcode Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi ISS2 M Multiply and Multiply Accumulate to Data Register LEGEND Dreg half determines which halves of the input operand registers to use Dreg half Dreg_lo Dreg_...

Page 894: ...0 1 0 x x x 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A1 A0 Negate Two s Complement 0xC42E 403F 1 1 0 0 0 1 0 x x x 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 A1 A1 Negate Two s Complement 0xC40E C...

Page 895: ...Dreg Dreg_lo SIGNBITS Dreg Sign Bit 0xC605 4000 0xC605 4E07 1 1 0 0 0 1 1 0 0 x x 0 0 1 0 1 0 1 0 0 Dest Dreg x x x 0 0 0 Source Dreg Dreg_lo SIGNBITS Dreg_lo Sign Bit 0xC605 8000 0xC605 8E07 1 1 0 0...

Page 896: ...ource 1 Dreg Dreg_lo Dreg_lo Dreg_lo NS Subtract 0xC403 4000 0xC403 4E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 1 1 0 1 0 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_lo Dreg_lo Dreg_hi NS Subtract 0xC403...

Page 897: ...S Subtract 0xC403 2000 0xC403 2E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 1 1 0 0 1 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_lo Dreg_lo Dreg_lo S Subtract 0xC403 6000 0xC403 6E3F 1 1 0 0 0 1 0 x x x 0...

Page 898: ..._hi S Subtract 0xC423 A000 0xC423 AE3F 1 1 0 0 0 1 0 x x x 1 0 0 0 1 1 1 0 1 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg_hi Dreg_hi Dreg_lo S Subtract 0xC423 E000 0xC423 EE3F 1 1 0 0 0 1 0 x x...

Page 899: ...0 1 0 0 1 0 0 SSYNC Force Emulation 0x0025 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 EMUEXCPT Disable Interrupts 0x0030 0x0037 0 0 0 0 0 0 0 0 0 0 1 1 Dreg CLI Dreg Enable Interrupts 0x0040 0x0047 0 0 0 0 0 0...

Page 900: ...No Op 0xC803 1800 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 MNOP when issued in parallel with two compatible load store instructions Abort 0x002F 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1...

Page 901: ...6 5 4 3 2 1 0 Data Cache Prefetch 0x0240 0x0247 0 0 0 0 0 0 1 0 0 1 0 0 0 Preg PREFETCH Preg Data Cache Prefetch 0x0260 0x0267 0 0 0 0 0 0 1 0 0 1 1 0 0 Preg PREFETCH Preg Data Cache Flush 0x0250 0x0...

Page 902: ...800 0xC60D 8E3F0 1 1 0 0 0 1 1 0 0 x x 0 1 1 0 1 1 0 0 0 Dest Dreg x x x Source 0 Dreg Source 1 Dreg Dreg ALIGN24 Dreg Dreg Disable Alignment Exception for Load 0xC412 C000 1 1 0 0 0 1 0 x x x 0 1 0...

Page 903: ...p Dreg Dest of A0 Op Dreg 1 1 1 1 1 1 NOTE When issuing compatible load store instructions in parallel with a Dual 16 Bit Accumulator Extraction with Addition instruction add 0x0800 0000 to the Dual 1...

Page 904: ...0 0 0 Source 0 Dreg Source 1 Dreg NOTE When issuing compatible load store instructions in parallel with a Quad 8 Bit Average Byte instruction add 0x0800 0000 to the Quad 8 Bit Average Byte opcode Dre...

Page 905: ...x 0 1 0 1 1 0 0 1 1 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg BYTEOP2P Dreg_pair Dreg_pair TL R Quad 8 Bit Average Half Word 0xC436 6000 0xC436 7E3F 1 1 0 0 0 1 0 x x x 1 1 0 1 1 0 0 1 1 0 De...

Page 906: ...ir Quad 8 Bit Subtract Abso lute Accumulate 0xC412 2000 0xC412 203F 1 1 0 0 0 1 0 x x x 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 Source 0 Dreg Source 1 Dreg NOTE When issuing compatible load store instructions...

Page 907: ...g Dreg VIT_MAX Dreg Dreg ASR Compare Select VIT_MAX 0xC609 8000 0xC609 8E07 1 1 0 0 0 1 1 0 0 x x 0 1 0 0 1 1 0 0 0 Dest Dreg x x x Source 0 Dreg Source 1 Dreg Dreg VIT_MAX Dreg Dreg ASL Compare Selec...

Page 908: ...Dreg SC0 Vector Add Subtract 0xC400 8000 0xC400 8E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 0 0 1 0 0 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg Dreg Dreg Vector Add Subtract 0xC400 A000 0xC400 AE3F 1 1...

Page 909: ...Vector Add Subtract 0xC400 7000 0xC400 7E3F 1 1 0 0 0 1 0 x x x 0 0 0 0 0 0 0 1 1 1 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg Dreg Dreg SC0 Vector Add Subtract 0xC400 C000 0xC400 CE3F 1 1 0 0...

Page 910: ...0xC401 C000 0xC401 CFFF 1 1 0 0 0 1 0 x x x 0 0 0 0 0 1 1 1 0 0 Dest 1 Dreg Dest 0 Dreg Source 0 Dreg Source 1 Dreg Dreg Dreg Dreg Dreg Dreg Dreg ASL Vector Add Subtract 0xC401 2000 0xC401 2FFF 1 1 0...

Page 911: ...Subtract 0xC401 3000 0xC401 3FFF 1 1 0 0 0 1 0 x x x 0 0 0 0 0 1 0 0 1 1 Dest 1 Dreg Dest 0 Dreg Source 0 Dreg Source 1 Dreg Dreg Dreg Dreg Dreg Dreg Dreg SCO Vector Add Subtract 0xC401 B000 0xC401 B...

Page 912: ...d Subtract 0xC421 A000 0xC421 AFFF 1 1 0 0 0 1 0 x x x 1 0 0 0 0 1 1 0 1 0 Dest 1 Dreg Dest 0 Dreg Source 0 Dreg Source 1 Dreg Dreg Dreg Dreg Dreg Dreg Dreg S ASR Vector Add Subtract 0xC421 E000 0xC42...

Page 913: ...SCO ASR Vector Add Subtract 0xC421 F000 0xC421 FFFF 1 1 0 0 0 1 0 x x x 1 0 0 0 0 1 1 1 1 1 Dest 1 Dreg Dest 0 Dreg Source 0 Dreg Source 1 Dreg Dreg Dreg Dreg Dreg Dreg Dreg SCO ASL Vector Add Subtrac...

Page 914: ...metic Shift 0xC681 0100 0xC681 0FFF 1 1 0 0 0 1 1 0 1 x x 0 0 0 0 1 0 0 0 0 Dest Dreg 2 s complement of uimm5 Source Dreg Dreg Dreg uimm5 V Vector Arithmetic Shift 0xC681 4000 0xC681 4EFF 1 1 0 0 0 1...

Page 915: ...0 0 0 1 1 0 0 0 0 0 Dest Dreg 0 0 0 Source 0 Dreg Source 1 Dreg Dreg MAX Dreg Dreg V Vector Minimum 0xC406 4000 0xC406 4E3F 1 1 0 0 0 1 0 x x x 0 0 0 1 1 0 0 1 0 0 Dest Dreg 0 0 0 Source 0 Dreg Sourc...

Page 916: ...c_reg_ 1 Dreg Dreg_lo Dreg_lo_hi Dreg_lo_hi Dreg_hi Dreg_lo_hi Dreg_lo_hi T Vector Multiply 0xC2C4 2000 0xC2C4 E7FF 1 1 0 0 0 0 1 0 1 1 0 0 0 1 0 0 Dreg half 1 1 0 0 Dreg half 0 Dest Dreg src_reg_ 0 D...

Page 917: ...1 Dreg Dreg_lo Dreg_lo_hi Dreg_lo_hi Dreg_hi Dreg_lo_hi Dreg_lo_hi FU M Vector Multiply 0xC314 2000 0xC314 E7FF 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 Dreg half 1 1 0 0 Dreg half 0 Dest Dreg src_reg_ 0 Dreg...

Page 918: ...eg_lo_hi ISS2 M Vector Multiply 0xC374 2000 0xC374 E7FF 1 1 0 0 0 0 1 1 0 1 1 1 0 1 0 0 Dreg half 1 1 0 0 Dreg half 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg NOTE When issuing compatible load store...

Page 919: ...Dreg Dreg_even Dreg_lo_hi Dreg_lo_hi Dreg_odd Dreg_lo_hi Dreg_lo_hi S2RND Vector Multiply 0xC32C 2000 0xC32C E7FF 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 0 Dreg half 1 1 0 0 Dreg half 0 Dest Dreg src_reg_ 0 Dre...

Page 920: ...lo_hi S2RND M Vector Multiply 0xC33C 2000 0xC33C E7FF 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 Dreg half 1 1 0 0 Dreg half 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg NOTE When issuing compatible load store in...

Page 921: ...and src_reg_1 Dreg encodes the input operand register to the right of the operand Vector Multiply and Multiply Accumulate NOTE When issuing compatible load store instructions in parallel with a Vector...

Page 922: ...iply and Multiply Accumulate 0xC010 0000 0xC013 DE3F 1 1 0 0 0 0 0 0 0 0 0 1 0 0 op1 Dreg half 1 0 op0 Dreg half 0 0 0 0 src_reg_ 0 Dreg src_reg_ 1 Dreg A0 or Dreg_lo_hi Dreg_lo_hi A1 or Dreg_lo_hi Dr...

Page 923: ...half 1 Dreg_lo Dreg_lo 0 0 Dreg_lo Dreg_hi 0 1 Dreg_hi Dreg_lo 1 0 Dreg_hi Dreg_hi 1 1 src_reg_0 Dreg encodes the input operand register to the left of the operand src_reg_1 Dreg encodes the input op...

Page 924: ...eg Dreg_lo A0 or Dreg_lo_hi Dreg_lo_hi Dreg_hi A1 or Dreg_lo_hi Dreg_lo_hi IS Vector Multiply and Multiply Accumulate 0xC184 2000 0xC187 FFFF 1 1 0 0 0 0 0 1 1 0 0 0 0 1 op1 Dreg half 1 1 op0 Dreg hal...

Page 925: ...lo A0 or Dreg_lo_hi Dreg_lo_hi Dreg_hi A1 or Dreg_lo_hi Dreg_lo_hi IH Vector Multiply and Multiply Accumulate 0xC014 2000 0xC017 FFFF 1 1 0 0 0 0 0 0 0 0 0 1 0 1 op1 Dreg half 1 1 op0 Dreg half 0 Dest...

Page 926: ...2000 0xC0D7 FFFF 1 1 0 0 0 0 0 0 1 1 0 1 0 1 op1 Dreg half 1 1 op0 Dreg half 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_lo A0 or Dreg_lo_hi Dreg_lo_hi Dreg_hi A1 or Dreg_lo_hi Dreg_lo_hi TFU M...

Page 927: ...tiply and Multi ply Accumulate instruction add 0x0800 0000 to the Vector Multiply and Multiply Accumulate opcode NOTE The ranges of these vector opcodes naturally overlaps with the component scalar Mu...

Page 928: ...0 0 Dreg_lo Dreg_hi 0 1 Dreg_hi Dreg_lo 1 0 Dreg_hi Dreg_hi 1 1 Dest Dreg encodes the destination Data Register src_reg_0 Dreg encodes the input operand register to the left of the operand src_reg_1...

Page 929: ...en A0 or Dreg_lo_hi Dreg_lo_hi Dreg_odd A1 or Dreg_lo_hi Dreg_lo_hi IS Vector Multiply and Multiply Accumulate 0xC02C 2000 0xC02F FFFF 1 1 0 0 0 0 0 0 0 0 1 0 1 1 op1 Dreg half 1 1 op0 Dreg half 0 Des...

Page 930: ...0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg Dreg_even A0 or Dreg_lo_hi Dreg_lo_hi Dreg_odd A1 or Dreg_lo_hi Dreg_lo_hi S2RND M Vector Multiply and Multiply Accumulate 0xC13C 2000 0xC13F FFFF 1 1 0 0 0...

Page 931: ...Dreg_lo Dreg_hi 0 1 Dreg_hi Dreg_lo 1 0 Dreg_hi Dreg_hi 1 1 Dest Dreg encodes the destination Data Register src_reg_0 Dreg encodes the input operand register to the left of the operand src_reg_1 Dreg...

Page 932: ...e 0xC104 0000 0xC107 DFFF 1 1 0 0 0 0 0 1 0 0 0 0 0 1 op1 Dreg half 1 0 op0 Dreg half 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg A0 or Dreg_lo_hi Dreg_lo_hi Dreg_hi A1 or Dreg_lo_hi Dreg_lo_hi IS Vec...

Page 933: ...r Multiply and Multi ply Accumulate instruction add 0x0800 0000 to the Vector Multiply and Multiply Accumulate opcode NOTE The ranges of these vector opcodes naturally overlaps with the component scal...

Page 934: ...o 0 0 Dreg_lo Dreg_hi 0 1 Dreg_hi Dreg_lo 1 0 Dreg_hi Dreg_hi 1 1 Dest Dreg encodes the destination Data Register src_reg_0 Dreg encodes the input operand register to the left of the operand src_reg_1...

Page 935: ...C 0000 0xC10F DFFF 1 1 0 0 0 0 0 1 0 0 0 0 1 1 op1 Dreg half 1 0 op0 Dreg half 0 Dest Dreg src_reg_ 0 Dreg src_reg_ 1 Dreg A0 or Dreg_lo_hi Dreg_lo_hi Dreg_odd A1 or Dreg_lo_hi Dreg_lo_hi IS Vector Mu...

Page 936: ...Vector Multiply and Multi ply Accumulate instruction add 0x0800 0000 to the Vector Multiply and Multiply Accumulate opcode NOTE The ranges of these vector opcodes naturally overlaps with the component...

Page 937: ...A0 and Dreg half 1 controls MAC1 oper ating on A1 Dreg half 0 and Dreg half 1 Dreg_lo Dreg_lo 0 0 Dreg_lo Dreg_hi 0 1 Dreg_hi Dreg_lo 1 0 Dreg_hi Dreg_hi 1 1 Dest Dreg encodes the destination Data Reg...

Page 938: ...g_hi Vector Pack 0xC604 8000 0xC604 8E3F 1 1 0 0 0 1 1 0 0 x x 0 0 1 0 0 1 0 0 0 Dest Dreg x x x Source 0 Dreg Source 1 Dreg Dreg PACK Dreg_hi Dreg_lo Vector Pack 0xC604 C000 0xC604 CE3F 1 1 0 0 0 1 1...

Page 939: ...Dest 0 Dreg Source Dreg 0 0 0 Dreg Dreg SEARCH Dreg LT Vector Search 0xC40D C000 0xC40D EFF8 1 1 0 0 0 1 0 x x x 0 0 1 1 0 1 1 1 0 0 Dest 1 Dreg Dest 0 Dreg Source Dreg 0 0 0 NOTE When issuing compati...

Page 940: ...Opcode Instructions Sheet 1 of 14 Instruction and Version Opcode Range No Op NOP 0x0000 Return RTS 0x0010 Return RTI 0x0011 Return RTX 0x0012 Return RTN 0x0013 Return RTE 0x0014 Idle IDLE 0x0020 Core...

Page 941: ...TSET Preg 0x00B0 0x00B5 Pop mostreg SP 0x0100 0x013F Push SP allreg 0x0140 0x017F Move CC Dreg CC 0x0200 0x0207 Move CC CC Dreg 0x0208 0x020F Negate CC CC CC 0x0218 Data Cache Prefetch PREFETCH Preg 0...

Page 942: ...033F Move CC CC statbit 0x0340 0x035F Move CC CC statbit 0x0360 0x037F Move CC statbit CC 0x0380 0x039F Move CC statbit CC 0x03A0 0x03BF Move CC statbit CC 0x03C0 0x03DF Move CC statbit CC 0x03E0 0x03...

Page 943: ...onditional IF CC Dreg Preg 0x0740 0x077F Move Conditional IF CC Preg Dreg 0x0780 0x07BF Move Conditional IF CC Preg Preg 0x07C0 0x07FF Compare Data Register CC Dreg Dreg 0x0800 0x083F Compare Pointer...

Page 944: ...er CC Dreg imm3 0x0C00 0x0C3F Compare Pointer Register CC Preg imm3 0x0C40 0x0C7F Compare Data Register CC Dreg imm3 0x0C80 0x0CBF Compare Pointer Register CC Preg imm3 0x0CC0 0x0CFF Compare Data Regi...

Page 945: ...egister genreg genreg genreg dagreg dagreg genreg dagreg dagreg genreg USP USP genreg Dreg sysreg sysreg Dreg sysreg Preg sysreg USP 0x3000 0x3FFF Arithmetic Shift Dreg Dreg 0x4000 0x403F Logical Shif...

Page 946: ...340 0x437F Negate Two s Complement Dreg Dreg 0x4380 0x43BF NOT One s Complement Dreg Dreg 0x43C0 0x43FF Modify Decrement Preg Preg 0x4400 0x443F Logical Shift Preg Preg 2 0x4440 0x447F Logical Shift P...

Page 947: ...FF OR Dreg Dreg Dreg 0x5600 0x57FF Exclusive OR Dreg Dreg Dreg 0x5800 0x59FF Add Preg Preg Preg 0x5A00 0x5BFF Logical Shift Preg Preg 1 0x5A00 0x5BFF NOTE The special case of the Preg Preg Preg Add in...

Page 948: ...Load High Data Register Half Dreg_hi W Preg 0x8400 0x85FF Load High Data Register Half Dreg_hi W Preg Preg 0x8401 0x85FE Load Half Word Zero Extended Dreg W Preg Preg Z 0x8601 0x87FE Load Half Word Si...

Page 949: ...Preg Dreg 0x9200 0x923F Store Pointer Register Preg Preg 0x9240 0x927F Store Data Register Preg Dreg 0x9280 0x92BF Store Pointer Register Preg Preg 0x92C0 0x92FF Store Data Register Preg Dreg 0x9300 0...

Page 950: ...xtended Dreg B Preg Z 0x9800 0x983F Load Byte Sign Extended Dreg B Preg X 0x9840 0x987F Load Byte Zero Extended Dreg B Preg Z 0x9880 0x98BF Load Byte Sign Extended Dreg B Preg X 0x98C0 0x98FF Load Byt...

Page 951: ...Load High Data Register Half Dreg_hi W Ireg 0x9D40 0x9D5F Load Data Register Dreg Ireg Mreg 0x9D80 0x9DFF Store Data Register Ireg Dreg 0x9E00 0x9E1F Store Low Data Register Half W Ireg Dreg_lo 0x9E20...

Page 952: ...3 Subtract Immediate Ireg 2 0x9F64 0x9F67 Add Immediate Ireg 4 0x9F68 0x9F6B Subtract Immediate Ireg 4 0x9F6C 0x9F6F Store Data Register Ireg Mreg Dreg 0x9F80 0x9FFF Load Data Register Dreg Preg uimm6...

Page 953: ...oad Data Register Dreg FP uimm7m4 0xB800 0xB9F7 Load Pointer Register Preg FP uimm7m4 0xB808 0xB9FF Store Data Register FP uimm7m4 Dreg 0xBA00 0xBBF7 Store Pointer Register FP uimm7m4 Preg 0xBA08 0xBB...

Page 954: ...ccumulate to Accumulator A1 Dreg_lo_hi Dreg_lo_hi 0xC001 1800 0xC001 D83F Multiply and Multiply Accumulate to Accumulator A1 Dreg_lo_hi Dreg_lo_hi 0xC002 1800 0xC002 D83F Multiply and Multiply Accumul...

Page 955: ...reg_hi A1 Dreg_lo A0 0xC007 3800 0xC007 39C0 Multiply and Multiply Accumulate to Data Register Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi 0xC008 1800 0xC008 D9FF Vector Multiply and Multiply Accumulate Dreg_ev...

Page 956: ...Dreg_lo_hi Dreg_lo_hi M 0xC014 2000 0xC017 FFFF Multiply and Multiply Accumulate to Half Register Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi M 0xC015 1800 0xC015 D9FF Multiply and Multiply Accumulate to Half R...

Page 957: ...i Dreg_lo_hi S2RND 0xC026 1800 0xC026 D9FF Move Register Half Dreg_hi A1 S2RND 0xC027 1800 0xC027 19C0 Move Register Half Dreg_lo A0 Dreg_hi A1 S2RND Dreg_hi A1 Dreg_lo A0 S2RND 0xC027 3800 0xC027 39C...

Page 958: ...ta Register Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi S2RND M 0xC039 1800 0xC039 D9FF Multiply and Multiply Accumulate to Data Register Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi S2RND M 0xC03A 1800 0xC03A D9FF Vector...

Page 959: ...i Dreg_lo_hi T M 0xC055 1800 0xC055 D9FF Multiply and Multiply Accumulate to Half Register Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi T M 0xC056 1800 0xC056 D9FF Vector Multiply and Multiply Accumulate A0 or Dr...

Page 960: ...lo A0 or Dreg_lo_hi Dreg_lo_hi A1 or Dreg_lo_hi Dreg_lo_hi FU 0xC080 2000 0xC083 FFFF Multiply and Multiply Accumulate to Accumulator A1 Dreg_lo_hi Dreg_lo_hi FU 0xC081 1800 0xC081 D83F Multiply and M...

Page 961: ...Dreg_hi A1 FU 0xC087 1800 0xC087 19C0 Move Register Half Dreg_lo A0 Dreg_hi A1 FU Dreg_hi A1 Dreg_lo A0 FU 0xC087 3800 0xC087 39C0 Multiply and Multiply Accumulate to Data Register Dreg_odd A1 Dreg_lo...

Page 962: ...reg_lo_hi Dreg_lo_hi FU M 0xC096 1800 0xC096 D9FF Multiply and Multiply Accumulate to Data Register Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi FU M 0xC098 1800 0xC098 D9FF Multiply and Multiply Accumulate to D...

Page 963: ...Accumulate to Half Register Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi TFU M 0xC0D6 1800 0xC0D6 D9FF Vector Multiply and Multiply Accumulate A0 or Dreg_lo_hi Dreg_lo_hi A1 or Dreg_lo_hi Dreg_lo_hi IS 0xC100 00...

Page 964: ...eg_lo_hi Dreg_hi A1 or Dreg_lo_hi Dreg_lo_hi IS 0xC104 2000 0xC107 FFFF Multiply and Multiply Accumulate to Half Register Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi IS 0xC105 1800 0xC105 D9FF Multiply and Multi...

Page 965: ...eg_hi A1 or Dreg_lo_hi Dreg_lo_hi IS M 0xC114 2000 0xC117 FFFF Multiply and Multiply Accumulate to Half Register Dreg_hi A1 Dreg_lo_hi Dreg_lo_hi IS M 0xC115 1800 0xC115 D9FF Multiply and Multiply Acc...

Page 966: ...ove Register Half Dreg_lo A0 Dreg_hi A1 ISS2 Dreg_hi A1 Dreg_lo A0 ISS2 0xC127 3800 0xC127 39C0 Multiply and Multiply Accumulate to Data Register Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi ISS2 0xC128 1800 0xC...

Page 967: ...Dreg_odd A1 Dreg_lo_hi Dreg_lo_hi ISS2 M 0xC13A 1800 0xC13A D9FF Vector Multiply and Multiply Accumulate Dreg_even A0 or Dreg_lo_hi Dreg_lo_hi Dreg_odd A1 or Dreg_lo_hi Dreg_lo_hi ISS2 M 0xC13C 2000...

Page 968: ..._lo_hi Dreg_lo_hi IH M 0xC176 1800 0xC176 D9FF Multiply and Multiply Accumulate to Half Register Dreg_lo A0 Dreg_lo_hi Dreg_lo_hi IU 0xC183 2000 0xC183 27FF Multiply and Multiply Accumulate to Half Re...

Page 969: ..._hi A1 Dreg_lo_hi Dreg_lo_hi IU M 0xC196 1800 0xC196 D9FF Multiply 16 Bit Operands Dreg_lo Dreg_lo_hi Dreg_lo_hi 0xC200 2000 0xC200 27FF Multiply 16 Bit Operands Dreg_hi Dreg_lo_hi Dreg_lo_hi 0xC204 0...

Page 970: ...27FF Multiply 16 Bit Operands Dreg_odd Dreg_lo_hi Dreg_lo_hi S2RND 0xC22C 0000 0xC22C C1FF Vector Multiply Dreg_even Dreg_lo_hi Dreg_lo_hi Dreg_odd Dreg_lo_hi Dreg_lo_hi S2RND 0xC22C 2000 0xC22C E7FF...

Page 971: ...E7FF Multiply 16 Bit Operands Dreg_even Dreg_lo_hi Dreg_lo_hi FU 0xC288 2000 0xC288 27FF Multiply 16 Bit Operands Dreg_odd Dreg_lo_hi Dreg_lo_hi FU 0xC28C 0000 0xC28C C1FF Vector Multiply Dreg_even D...

Page 972: ...ctor Multiply Dreg_lo Dreg_lo_hi Dreg_lo_hi Dreg_hi Dreg_lo_hi Dreg_lo_hi IS 0xC304 2000 0xC304 E7FF Multiply 16 Bit Operands Dreg_even Dreg_lo_hi Dreg_lo_hi IS 0xC308 2000 0xC308 27FF Multiply 16 Bit...

Page 973: ...FF Multiply 16 Bit Operands Dreg_hi Dreg_lo_hi Dreg_lo_hi ISS2 M 0xC334 0000 0xC334 C1FF Vector Multiply Dreg_lo Dreg_lo_hi Dreg_lo_hi Dreg_hi Dreg_lo_hi Dreg_lo_hi ISS2 M 0xC334 2000 0xC334 E7FF Mult...

Page 974: ...4 C1FF Vector Multiply Dreg_lo Dreg_lo_hi Dreg_lo_hi Dreg_hi Dreg_lo_hi Dreg_lo_hi IU M 0xC394 2000 0xC394 E7FF Vector Add Subtract Dreg Dreg Dreg 0xC400 0000 0xC400 0E3F Vector Add Subtract Dreg Dreg...

Page 975: ...Dreg Dreg 0xC401 0000 0xC401 0FFF Vector Add Subtract Dreg Dreg Dreg Dreg Dreg Dreg CO 0xC401 1000 0xC401 1FFF Vector Add Subtract Dreg Dreg Dreg Dreg Dreg Dreg S 0xC401 2000 0xC401 2FFF Vector Add S...

Page 976: ...0xC402 4000 0xC402 4E3F Add Dreg_lo Dreg_lo Dreg_hi S 0xC402 6000 0xC402 6E3F Add Dreg_lo Dreg_hi Dreg_lo NS 0xC402 8000 0xC402 8E3F Add Dreg_lo Dreg_hi Dreg_lo S 0xC402 A000 0xC402 AE3F Add Dreg_lo...

Page 977: ...eg Dreg Dreg Dreg 0xC404 8000 0xC404 8FFF Vector Add Subtract Dreg Dreg Dreg Dreg Dreg Dreg S 0xC404 A000 0xC404 AFFF Add Subtract Prescale Up Dreg_lo Dreg Dreg RND12 0xC405 0000 0xC405 0E3F Add Subtr...

Page 978: ...7 EFC0 Load Immediate A0 0 0xC408 003F Saturate A0 A0 S 0xC408 203F Load Immediate A1 0 0xC408 403F Saturate A1 A1 S 0xC408 603F Load Immediate A1 A0 0 0xC408 803F Saturate A1 A1 S A0 A0 S 0xC408 A03F...

Page 979: ...g_hi SIGN Dreg_lo Dreg_lo 0xC40C 0000 0xC40C 0E38 Dual 16 Bit Accumulator Extraction with Addition Dreg A1 L A1 H Dreg A0 L A0 H 0xC40C 403F 0xC40C 4FC0 Round to Half Word Dreg_lo Dreg RND 0xC40C C000...

Page 980: ...0 Vector Add Subtract Dreg A0 A1 Dreg A0 A1 S 0xC411 603F 0xC411 6FC0 Quad 8 Bit Subtract Absolute Accumulate SAA Dreg_pair Dreg_pair 0xC412 0000 0xC412 003F Quad 8 Bit Subtract Absolute Accumulate SA...

Page 981: ...OP2P Dreg_pair Dreg_pair TL 0xC416 4000 0xC416 6E3F Quad 8 Bit Average Half Word Dreg BYTEOP2P Dreg_pair Dreg_pair TL R 0xC416 6000 0xC416 7E3F Dual 16 Bit Add Clip Dreg BYTEOP3P Dreg_pair Dreg_pair L...

Page 982: ...reg ASL 0xC421 C000 0xC421 CFFF Vector Add Subtract Dreg Dreg Dreg Dreg Dreg Dreg CO ASL 0xC421 D000 0xC421 DFFF Vector Add Subtract Dreg Dreg Dreg Dreg Dreg Dreg S ASL 0xC421 E000 0xC421 EFFF Vector...

Page 983: ...0xC423 AE3F Subtract Dreg_hi Dreg_hi Dreg_hi NS 0xC423 C000 0xC423 CE3F Subtract Dreg_hi Dreg_hi Dreg_hi S 0xC423 E000 0xC423 EE3F Add Subtract Prescale Up Dreg_hi Dreg Dreg RND12 0xC425 0000 0xC425 0...

Page 984: ...reg_pair TH 0xC436 4000 0xC436 6E3F Quad 8 Bit Average Half Word Dreg BYTEOP2P Dreg_pair Dreg_pair TH R 0xC436 6000 0xC436 7E3F Dual 16 Bit Add Clip Dreg BYTEOP3P Dreg_pair Dreg_pair HI 0xC437 0000 0x...

Page 985: ...Dreg_hi BY Dreg_lo 0xC600 B000 0xC600 BE3F Vector Arithmetic Shift Dreg ASHIFT Dreg BY Dreg_lo V 0xC601 0000 0xC601 0E3F Vector Arithmetic Shift Dreg ASHIFT Dreg BY Dreg_lo V S 0xC601 4000 0xC601 4E3...

Page 986: ...Dreg_hi Dreg_lo 0xC604 8000 0xC604 8E3F Vector Pack Dreg PACK Dreg_hi Dreg_hi 0xC604 C000 0xC604 CE3F Sign Bit Dreg_lo SIGNBITS Dreg 0xC605 0000 0xC605 0E07 Sign Bit Dreg_lo SIGNBITS Dreg_lo 0xC605 40...

Page 987: ...g ASL 0xC609 8000 0xC609 8E07 Compare Select VIT_MAX Dreg VIT_MAX Dreg Dreg ASR 0xC609 C000 0xC609 CE07 Bit Field Extraction Dreg EXTRACT Dreg Dreg_lo Z 0xC60A 0000 0xC60A 0E3F Bit Field Extraction Dr...

Page 988: ...Dreg_hi uimm4 0xC680 3180 0xC680 3FFF Arithmetic Shift Dreg_lo Dreg_lo uimm4 S 0xC680 4000 0xC680 4E7F Arithmetic Shift Dreg_lo Dreg_hi uimm4 S 0xC680 5000 0xC680 5E7F Arithmetic Shift Dreg_hi Dreg_l...

Page 989: ...0xC681 8E7F Vector Logical Shift Dreg Dreg uimm4 V 0xC681 8180 0xC681 8FFF Arithmetic Shift Dreg Dreg uimm5 0xC682 0100 0xC682 0FFF Arithmetic Shift Dreg Dreg uimm5 S 0xC682 4000 0xC680 4EFF Logical...

Page 990: ...the address of LOOP_BEGIN determines pcrel5m2 and the address of LOOP_END determines pcrel11m2 0xE080 0000 0xE08F 03FF Zero Overhead Loop Setup LOOP loop_name LC1 LOOP_BEGIN loop_name LOOP_END loop_n...

Page 991: ...el5m2 and the address of LOOP_END determines pcrel11m2 0xE0E0 0000 0xE0AF F3FF Zero Overhead Loop Setup LOOP loop_name LC1 Preg 1 LOOP_BEGIN loop_name LOOP_END loop_name is mapped to LSETUP pcrel5m2 p...

Page 992: ...mm17m4 0xE500 0000 0xE53F 7FFF Load Pointer Register Preg Preg uimm17m4 0xE500 8000 0xE53F FFFF Load Half Word Sign Extended Dreg W Preg uimm16m2 X 0xE540 0000 0xE57F 8FFF Load Half Word Sign Extended...

Page 993: ...Byte B Preg uimm15 Dreg 0xE680 8000 0xE6BF FFFF Store Pointer Register Preg uimm17m4 Preg 0xE700 0000 0xE7EF 8FFF Store Pointer Register Preg uimm17m4 Preg 0xE700 8000 0xE73F FFFF Linkage LINK uimm18...

Page 994: ...Instructions Listed By Operation Code C 194 ADSP BF53x BF56x Blackfin Processor Programming Reference...

Page 995: ...efore the value of an unsigned integer is interpreted in the usual binary sense The least significant words of multi ple precision numbers are treated as unsigned numbers Signed numbers supported by t...

Page 996: ...al 1 M format and an unsigned fractional 0 N format where N is the num ber of bits in the data word and M N 1 The notation used to describe a format consists of two numbers separated by a period the f...

Page 997: ...meric Formats Figure D 2 Example of Fractional Format Signed Fractional 13 3 Bit Weight Sign Bit Radix Point 0 1 2 15 14 13 2 3 2 2 2 1 210 211 212 3 4 20 21 Unsigned Fractional 13 3 Bit Weight Sign B...

Page 998: ...687500 4 0 0 000122070312500 4 12 4 12 7 999755859375000 8 0 0 000244140625000 5 11 5 11 15 999511718750000 16 0 0 000488281250000 6 10 6 10 31 999023437500000 32 0 0 000976562500000 7 9 7 9 63 998046...

Page 999: ...family assembly language allows you to specify whether the inputs are both signed both unsigned or one of each mixed mode The location of the radix point in the result can be derived from its location...

Page 1000: ...sign bit when both operands are signed yielding a result that is cor rectly formatted When both operands are in 1 15 format the result is 2 30 30 fractional bits A left shift causes the multiplier res...

Page 1001: ...n the two guard bits then the process can be run without loss of data Later however the block must be adjusted to replace the guard bits before the next process Figure D 5 shows the data after process...

Page 1002: ...In either case the block exponent is updated to reflect the shift Figure D 5 Block Floating point Adjustment Sign Bit One Guard Bit 0x1FFF 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0x3FFF 0 0 1 1 1 1 1 1 1 1 1...

Page 1003: ...15 67 32 bit ALU MAC instructions parallel 20 3 32 bit operations 2 29 A A0 accumulator register 2 2 A0 overflow AV0 bit 2 25 A1 accumulator register 2 2 A1 overflow AV1 bit 2 25 AAU address arithmet...

Page 1004: ...t post modify pre modify DAG data address generator bit reversed addresses 5 15 circular buffer 5 12 indexed 5 8 modes 5 18 addressing continued post modify 5 11 pre modify stack pointer 5 11 transfer...

Page 1005: ...S0 sticky overflow A0 C 7 AVS1 sticky overflow A1 C 7 AZ zero C 7 CC control code bit C 7 arithmetic status flags continued on ADSP BF535 A 2 summarized 1 15 V overflow D register 1 17 C 7 VS sticky o...

Page 1006: ...example 2 52 bit set example 2 52 bit test example 2 52 bit toggle example 2 52 bit multiplex BITMUX instruction See BITMUX BITMUX bit multiplex instruction C 45 bit operations instructions 13 1 C 44...

Page 1007: ...verage half word instruction 18 24 BYTEOP3P dual 16 bit add clip instruction 18 8 BYTEPACK quad 8 bit pack instruction 18 30 BYTEUNPACK quad 8 bit unpack instruction 18 41 C cache address collision 6...

Page 1008: ...er registers listed 1 21 disabling 1 14 1 21 1 22 C 3 circular addressing continued enabling 1 22 example instructions 1 22 initializing buffer registers 8 11 8 24 8 28 8 42 8 46 8 50 load data regist...

Page 1009: ...n 6 69 instructions 2 24 4 3 JUMP instruction 4 10 register move 4 20 speculative load execution example 6 69 condition code CC bit See CC bit condition code CC flag bit 4 18 constants imm16 8 4 imm3...

Page 1010: ...tructions one s population count 13 26 count value WPDACNT 15 0 field 21 12 count value WPIACNT 15 0 field 21 7 CPLB_DIRTY bit 6 57 CPLB_L1_AOW bit 6 57 CPLB_L1_CHBL bit 6 55 6 57 CPLB_LOCK bit 6 55 6...

Page 1011: ...ata bank access bit 6 40 data banks configuration 6 30 data cache access 6 33 control instructions 6 37 flush instruction C 101 data cache continued invalidation 6 38 L1 memory 6 2 6 29 data cacheabil...

Page 1012: ...g features 21 1 DEC instruction decode 4 7 DEC stage 4 9 deferring exception processing 4 68 DEPOSIT bit field deposit instruction 13 10 DF1 data fetch 1 4 7 DF2 data fetch 2 4 7 DF2 stage 4 9 direct...

Page 1013: ...bit operations defined with example 2 29 dual MAC operations example 2 47 DW 1 0 double word index field 6 21 6 40 dynamic power management controller DPMC See DPMC E EAB bus 6 8 6 14 EBIU external bu...

Page 1014: ...3 4 exception routine example code 4 70 exceptions address violations not flagged 17 3 to 17 9 alignment 7 3 8 8 to 8 50 10 3 10 7 10 10 10 15 10 19 alignment errors prevented 18 6 to 18 41 attempting...

Page 1015: ...nstruction 12 8 C 43 EXCPT force exception instruction 4 66 16 20 C 99 execute 1 EX1 4 7 execute 2 EX2 4 7 execution cycle count CYCLES and CYCLES2 registers 21 24 execution trace code examples 21 18...

Page 1016: ...ng and disabling interrupts 4 48 global interrupt disable bit 4 41 GSM global system for mobile communications speech compression routines 2 23 speech vocoder algorithms 2 41 H hardware loops 4 21 res...

Page 1017: ...he way lock field 6 5 6 7 6 17 IMASK core interrupt mask register 4 31 6 74 IMC L1 instruction memory configuration bit 6 6 6 7 6 19 IMEM_CONTROL instruction memory control register 6 5 6 47 imm16 con...

Page 1018: ...down C 58 add subtract prescale up C 59 add with shift C 46 AND C 43 arithmetic shift C 46 bit clear C 44 instruction opcodes continued bit field deposit C 44 bit field extraction C 44 bit multiplex...

Page 1019: ...43 one s population count C 45 OR C 43 pop C 37 pop multiple C 37 push C 37 push multiple C 37 quad 8 bit add C 103 instruction opcodes continued quad 8 bit average byte C 104 quad 8 bit average half...

Page 1020: ...17 2 instruction test registers 6 19 to 6 23 writing to 6 20 instruction watchpoint address control WPIACTL register 21 7 instruction watchpoint address count WPIACNTn registers 21 5 21 6 instruction...

Page 1021: ...es 4 32 using hardware loops 4 28 ITEST_COMMAND instruction test command register 6 21 ITEST_DATAx instruction test data registers 6 22 17 2 IVGn bits 4 39 4 40 4 41 IVHW hardware error bit 4 39 4 40...

Page 1022: ...L1 instruction memory about 6 3 address alignment 6 7 data cache 6 29 definition 6 75 frequency 6 4 overview 6 2 scratchpad data SRAM 6 4 level 2 L2 memory CCLK cycles 6 1 defined 1 5 6 43 enabling c...

Page 1023: ...stant 1 12 C 6 loop registers initialization 7 15 table of 4 22 zero overhead 4 6 loops branch instructions 7 18 buffer 4 24 conditions evaluation 4 22 counter register 7 17 disabling 4 23 loops conti...

Page 1024: ...ctor maximum 19 32 C 115 MAX vector maximum instruction 15 30 19 32 media access control See MAC memory See also cache level 1 L1 memory level 1 L1 data memory level 1 L1 instruction memory level 2 L2...

Page 1025: ...ify increment 15 37 C 61 modify registers M 3 0 5 8 DAGs and circular buffering 5 12 defined 1 14 description C 3 explained 5 3 function in circular addressing 1 21 load data register 8 10 modify decr...

Page 1026: ...67 C 86 multiply and multiply accumulate to half register instruction 15 58 C 74 multiply without accumulate 2 44 fractional unsigned operand example 2 45 unsigned integer operand example 2 45 N nega...

Page 1027: ...ction 13 26 opcodes See instruction opcodes operating modes 3 1 to 3 10 operators logical OR 12 6 logical OR assign 11 12 OR 12 6 vector add add 19 18 vector add subtract 19 18 vector subtract add 19...

Page 1028: ...er unsigned operator IU use with compare instructions 11 2 11 6 integer signed operator IS 9 16 integer unsigned operator IU 9 16 mixed mode M 19 38 19 41 option flags continued no saturate NS negate...

Page 1029: ...11 4 12 pcrelm2 7 2 PEMUSWx bits 21 20 21 21 pending event requests coordinating 4 38 performance monitor control PFCTL register 21 19 21 20 performance monitor counter PFCNTRn registers 21 19 21 20 p...

Page 1030: ...ioritization of events 1 6 priority watermark PRIO_MARK 0 3 field 6 36 processor single core bus architecture 6 2 processor core architecture diagram 1 2 2 2 processor mode determination 3 1 emulation...

Page 1031: ...rs D 4 reading MMRs restriction 3 1 read transfer address 6 14 read write access bit 6 40 read write access RW bit 6 21 real time clock RTC processor idle state 3 10 reg list of registers 8 4 register...

Page 1032: ...interrupt register return from interrupt RTI instruction See RTI return from NMI RTN instruction 7 10 return from nonmaskable interrupt RTN instruction 7 11 return from nonmaskable interrupt RTN inst...

Page 1033: ...tructions 15 53 saturate instruction 15 80 C 95 saturation 16 bit register range 1 18 32 bit register range 1 18 40 bit register range 1 18 saturation continued accumulator 1 12 defined 1 17 saving lo...

Page 1034: ...1 7 1 8 4 35 4 55 SIGN add on instruction 19 3 sign bit SIGNBITS instruction See SIGNBITS SIGNBITS sign bit instruction 15 83 C 95 signed fraction operands T multiply 16 bit operands instruction 15 43...

Page 1035: ...instructions C 37 stack pointer 1 13 10 7 to 10 19 C 2 stack pointer SP register 4 6 5 6 stalled load instruction 6 34 stalls computation 4 9 DAG 4 9 data memory 4 9 stalls continued pipeline 6 66 reg...

Page 1036: ...isor single step SSSTEP bit 21 26 supervisor stack preventing exceptions 4 56 supervisor stack pointer SP register 5 6 5 7 supply addressing 5 2 support technical or customer xxviii SWRST software res...

Page 1037: ...mendation for allocating 4 56 system synchronize instruction C 99 system synchronize SSYNC instruction 16 8 T tag definition 6 76 tag 1 0 field 6 23 tag 19 4 field 6 23 6 42 tag 3 2 field 6 23 6 42 ta...

Page 1038: ...ly 16 bit operands instruction 15 43 multiply and multiply accumulate to half register instruction 15 58 use with multiply instructions 15 43 15 58 unsigned integer D 1 unsigned numbers data formats 2...

Page 1039: ...r minimum MIN instruction 19 35 C 115 vector multiply and multiply accumulate instruction 19 41 C 121 vector multiply instruction 19 38 C 115 vector negate two s complement instruction 19 46 C 138 vec...

Page 1040: ...An data watchpoint address registers 21 10 WPDCNTEN0 bit 21 13 WPDCNTEN1 bit 21 13 WPDREN01 bit 21 13 WPDRINV01 bit 21 13 WPDSRC0 1 0 field 21 13 WPDSRC1 1 0 field 21 13 WPIACNTn instruction watchpoin...

Page 1041: ...X XOR exclusive OR instruction 2 26 12 8 Z zero extended Z flag use with instructions 13 16 zero extending data 2 12 zero overhead loop registers 4 6 zero overhead loops registers 4 22 setting up 7 1...

Page 1042: ...Index I 40 ADSP BF53x BF56x Blackfin Processor Programming Reference...

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