Analog Devices ADSP-BF53x Blackfin, Reference

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L1 Instruction Memory
6-10 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
L1 Instruction Cache
For information about cache terminology, see “Terminology” on page
6-74 .
The L1 Instruction Memory may also be configured to contain a, 4-Way
set associative instruction 16K byte cache. To improve the average access
latency for critical code sections, each Way or line of the cache can be
locked independently. When the memory is configured as cache, it cannot
be accessed directly.
When cache is enabled, only memory pages further specified as cacheable
by the CPLBs will be cached. When CPLBs are enabled, any memory
location that is accessed must have an associated page definition available,
or a CPLB exception is generated. CPLBs are described in
“Memory Pro-
tection and Properties” on page 6-45 .
Figure 6-4 on page 6-12 shows the overall Blackfin processor instruction
cache organization.
Cache Lines
As shown in Figure 6-4 , the cache consists of a collection of cache lines.
Each cache line is made up of a tag component and a data component.
• The tag component incorporates a 20-bit address tag, least recently
used (LRU) bits, a Valid bit, and a Line Lock bit.
• The data component is made up of four 64-bit words of instruction
data.
The tag and data components of cache lines are stored in the tag and data
memory arrays, respectively.