Analog Devices ADSP-BF53x Blackfin, Reference

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Interrupt Processing
4-48 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Interrupt Processing
The following sections describe interrupt processing.
Global Enabling/Disabling of Interrupts
General-purpose interrupts can be globally disabled with the
CLI Dreg
instruction and re-enabled with the
STI Dreg
instruction, both of which
are only available in Supervisor mode. Reset, NMI, emulation, and excep-
tion events cannot be globally disabled. Globally disabling interrupts
clears
IMASK[15:5]
after saving
IMASK
’s current state.
CLI R5; /* save IMASK to R5 and mask all */
/* place critical instructions here */
STI R5; /* restore IMASK from R5 again */
See “Enable Interrupts” and “Disable Interrupts” in Chapter 16, “External
Event Management.”
When multiple instructions need to be atomic or are too time-critical to
be delayed by an interrupt, disable the general-purpose interrupts, but be
sure to re-enable them at the conclusion of the code sequence.
Servicing Interrupts
The Core Event Controller (CEC) has a single interrupt queueing element
per event—a bit in the
ILAT
register. The appropriate
ILAT
bit is set when
an interrupt rising edge is detected (which takes two core clock cycles) and
cleared when the respective
IPEND
register bit is set. The
IPEND
bit indi-
cates that the event vector has entered the core pipeline. At this point, the
CEC recognizes and queues the next rising edge event on the correspond-
ing interrupt input. The minimum latency from the rising edge transition
of the general-purpose interrupt to the
IPEND
output assertion is three core
clock cycles. However, the latency can be much higher, depending on the
core’s activity level and state.