Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
18-34 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Options
The (R) syntax reverses the order of the source registers within each regis-
ter pair. Typical high performance applications cannot afford the
overhead of reloading both register pair operands to maintain byte order
for every calculation. Instead, they alternate and load only one register
pair operand each time and alternate between the forward and reverse byte
order versions of this instruction. By default, the low order bytes come
from the low register in the register pair. The (R) option causes the low
order bytes to come from the high register.
In the optional reverse source order case (for example, using the (R) syn-
tax), the only difference is the source registers swap places within the
register pair in their byte ordering. Assume that a source register pair con-
tains the data shown in
Table 18-27 .
The mnemonic derives its name from the fact that the operands are bytes,
the result is 16 bits, and the arithmetic operation is “minus” for
subtraction.
Table 18-27. I-register Bits and the Byte Alignment
The bytes selected are src_reg_pair_LO src_reg_pair_HI
Two LSB’s of I0 or I1 byte7 byte6 byte5 byte4 byte3 byte2 byte1 byte0
00b: byte3 byte2 byte1 byte0
01b: byte4 byte3 byte2 byte1
10b: byte5 byte4 byte3 byte2
11b: byte6 byte5 byte4 byte3