Analog Devices ADSP-BF53x Blackfin, Reference

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Arithmetic Logic Unit (ALU)
2-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Quad 16-Bit Operations
In quad 16-bit operations, any two 32-bit registers may be used as the
inputs to ALU0 and ALU1, considered as pairs of 16-bit operands. A
small number of addition or subtraction operations produces four 16-bit
results that are deposited into two arbitrary, 32-bit destination registers.
Both ALU0 and ALU1 are used for this operation. Because there are only
two 32-bit data paths from the Data Register File to the arithmetic units,
the same two pairs of 16-bit inputs are presented to ALU1 as to ALU0.
The instruction construct is identical to that of a dual 16-bit operation,
and input operands must be the same for both ALUs.
For example:
R3 = R0 +|+ R1, R2 = R0 –|– R1 (S) ;
performs four operations:
• Adds the 16-bit contents of
R1.H
(
R1
high half) to the 16-bit con-
tents of
R0.H (R0
high half) and deposits the result in
R3.H
with
saturation.
• Adds
R1.L
to
R0.L
and deposits the result in
R3.L
with saturation.
• Subtracts the 16-bit contents of
R1.H
(
R1
high half) from the 16-bit
contents of the
R0.H (R0
high half) and deposits the result in
R2.H
with saturation.
• Subtracts
R1.L
from
R0.L
and deposits the result in
R2.L
with
saturation.
Explicitly, the four equivalent instructions are:
R3.H = R0.H + R1.H (S) ;
R3.L = R0.L + R1.L (S) ;
R2.H = R0.H – R1.H (S) ;
R2.L = R0.L – R1.L (S) ;