Analog Devices ADSP-BF53x Blackfin, Reference

Page: 335 / 1042

ADSP-BF53x/BF56x Blackfin Processor Programming Reference 8-11
Load / Store
uimm6m4
: 6-bit unsigned field that must be a multiple of 4, with a range of
0 through 60 bytes
uimm7m4
: 7-bit unsigned field that must be a multiple of 4, with a range of
4 through 128 bytes
uimm17m4
: 17-bit unsigned field that must be a multiple of 4, with a range
of 0 through 131,068 bytes (0x0000 0000 through 0x0001 FFFC)
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length. Comment
(b) identifies 32-bit instruction length.
Functional Description
The Load Data Register instruction loads a 32-bit word into a 32-bit
D-register from a memory location. The Source Pointer register can be a
P-register, I-register, or the Frame Pointer.
The indirect address and offset must yield an even multiple of 4 to main-
tain 4-byte word address alignment. Failure to maintain proper alignment
causes a misaligned memory access exception.
L
The instruction versions that explicitly modify
Ireg
support
optional circular buffering. See “Automatic Circular Addressing”
on page 1-21 for more details. Unless circular buffering is desired,
disable it prior to issuing this instruction by clearing the Length
Register (
Lreg
) corresponding to the
Ireg
used in this instruction.
Example: If you use
I2
to increment your address pointer, first
clear
L2
to disable circular buffering. Failure to explicitly clear
Lreg
beforehand can result in unexpected Ireg values.
The circular address buffer registers (Index, Length, and Base) are
not initialized automatically by Reset. Traditionally, user software
clears all the circular address buffer registers during boot-up to dis-
able circular buffering, then initializes them later, if needed.