Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 12-11
Logical Operations
The Type I
LFSR
s (no feedback) applies a 32-bit registered mask to a
40-bit state residing in Accumulator
A0
, followed by a bit-wise XOR
reduction operation. The result is placed in CC and a destination register
half.
The Type I
LFSR
s (with feedback) applies a 40-bit mask in Accumulator
A1
to a 40-bit state residing in
A0
. The result is shifted into
A0
.
In the following circuits describing the BXOR instruction group, a
bit-wise XOR reduction is defined as:
where B
0
through B
N–1
represent the N bits that result from masking the
contents of Accumulator
A0
with the polynomial stored in either
A1
or a
32-bit register. The instruction descriptions are shown in Figure 12-1 .
In the figure above, the bits
A0
bit 0 and
A0
bit 1 are logically AND’ed
with bits D[0] and D[1]. The result from this operation is XOR reduced
according to the following formula.
Figure 12-1. Bit-Wise Exclusive-OR Reduction
Out B
( ( ( ( (
0
B
1
)
B
2
)
B
3
)
...
⊕ )
B
n 1
–
) ⊕ ⊕ ⊕ ⊕
=
D[0] D[1]
A0[0] A0[1]
s(D)
s D
( )
A0 0
[ ]
&
D 0
[ ] )
A0 1
[ ]
&
D 1
[ ] ( ⊕ ( )
=