Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 3-11
Operating Modes and States
Software in Supervisor or Emulation mode can invoke the Reset state
without involving the external
RESET
signal. This can be done by issuing
the Reset version of the
RAISE
instruction.
Application programs in User mode cannot invoke the Reset state, except
through a system call provided by an operating system kernel.
Table 3-5
summarizes the state of the processor upon reset.
Table 3-5. Processor State Upon Reset
Item Description of Reset State
Core
Operating Mode Supervisor mode in reset event, clocks stopped
Rounding Mode Unbiased rounding
Cycle Counters Disabled, zero
DAG Registers (I, L, B, M) Random values (must be cleared at initialization)
Data and Address Registers Random values (must be cleared at initialization)
IPEND, IMASK, ILAT Cleared, interrupts globally disabled with IPEND bit 4
CPLBs Disabled
L1 Instruction Memory SRAM (cache disabled)
L1 Data Memory SRAM (cache disabled)
Cache Validity Bits Invalid
System
Booting Methods Determined by the values of BMODE pins at reset
MSEL Clock Frequency Reset value = 10
PLL Bypass Mode Disabled
VCO/Core Clock Ratio Reset value = 1
VCO/System Clock Ratio Reset value = 5
Peripheral Clocks Disabled