Analog Devices ADSP-BF53x Blackfin, Reference

Page: 1000 / 1042

Block Floating-Point Format
D-6 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Fractional Mode And Integer Mode
A product of 2 two’s-complement numbers has two sign bits. Since one of
these bits is redundant, you can shift the entire result left one bit. Addi-
tionally, if one of the inputs was a 1.15 number, the left shift causes the
result to have the same format as the other input (with 16 bits of addi-
tional precision). For example, multiplying a 1.15 number by a 5.11
number yields a 6.26 number. When shifted left one bit, the result is a
5.27 number, or a 5.11 number plus 16 LSBs.
The ADSP-BF53x/BF56x Blackfin family provides a means (a signed frac-
tional mode) by which the multiplier result is always shifted left one bit
before being written to the result register. This left shift eliminates the
extra sign bit when both operands are signed, yielding a result that is cor-
rectly formatted.
When both operands are in 1.15 format, the result is 2.30 (30 fractional
bits). A left shift causes the multiplier result to be 1.31 which can be
rounded to 1.15. Thus, if you use a signed fractional data format, it is
most convenient to use the 1.15 format.
Block Floating-Point Format
A block floating-point format enables a fixed-point processor to gain some
of the increased dynamic range of a floating-point format without the
overhead needed to do floating-point arithmetic. However, some addi-
tional programming is required to maintain a block floating-point format.
A floating-point number has an exponent that indicates the position of the
radix point in the actual value. In block floating-point format, a set
(block) of data values share a common exponent. A block of fixed-point
values can be converted to block floating-point format by shifting each
value left by the same amount and storing the shift value as the block
exponent.