Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
18-38 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
In the default source order case (for example, not the (R) syntax), assume a
source register pair contain the data shown in
Table 18-29 .
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
Options
The (R) syntax reverses the order of the source registers within each pair.
Typical high performance applications cannot afford the overhead of
reloading both register pair operands to maintain byte order for every cal-
culation. Instead, they alternate and load only one register pair operand
each time and alternate between the forward and reverse byte order ver-
sions of this instruction. By default, the low order bytes come from the
low register in the register pair. The (R) option causes the low order bytes
to come from the high register.
When reversing source order by using the (R) syntax, the source registers
swap places within the register pair in their byte ordering. If a source reg-
ister pair contains the data shown in
Table 18-30 , then the SAA
instruction computes 12 pixel operations simultaneously–the three-opera-
tion subtract-absolute-accumulate on four pairs of operand bytes in
parallel.
Table 18-29. I-register Bits and the Byte Alignment
The bytes selected are src_reg_pair_HI src_reg_pair_LO
Two LSB’s of I0 or I1 byte7 byte6 byte5 byte4 byte3 byte2 byte1 byte0
00b: byte3 byte2 byte1 byte0
01b: byte4 byte3 byte2 byte1
10b: byte5 byte4 byte3 byte2
11b: byte6 byte5 byte4 byte3