Analog Devices ADSP-BF53x Blackfin, Reference

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Introduction
C-8 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Core Register Encoding Map
Instruction opcodes can address any core register by Register Group and
Register Number using the following encoding.
Opcode Representation
The Blackfin architecture accepts 16- and 32-bit opcodes. This document
represents the opcodes as hexadecimal values or ranges of values and as
binary bit fields.
Some instructions have no variable arguments, and therefore produce only
one hex value. The value appears in the “min” Hex Opcode Range col-
umn. Instructions that support variable arguments (such as a choice of
source or destination registers, optional modes, or constants) span a range
of hex values. The minimum and maximum allowable hex values are
shown in that case. As explained in
“Holes In Opcode Ranges” on
page C-10 , the instruction may not produce all possible hex values within
the range.
Table C-4. Core Register Encoding Map
REGISTER NUMBER
REGISTER
GROUP 0 1 2 3 4 5 6 7
0 R0 R1 R2 R3 R4 R5 R6 R7
1 P0 P1 P2 P3 P4 P5 SP FP
2 I0 I1 I2 I3 M0 M1 M2 M3
3 B0 B1 B2 B3 L0 L1 L2 L3
4 A0.x A0.w A1.x A1.w <res.> <res.> ASTAT RETS
5 <res.> <res.> <res.> <res.> <res.> <res.> <res.> <res.>
6 LC0 LT0 LB0 LC1 LT1 LB1 CYCLES CYCLES2
7 USP SEQSTAT SYSCFG RETI RETX RETN RETE EMUDAT