Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 15-39
Arithmetic Operations
See “Rounding and Truncating” on page 1-19 for a description of round-
ing behavior.
L
The instruction versions that explicitly modify
Ireg
support
optional circular buffering. See “Automatic Circular Addressing”
on page 1-21 for more details. Unless circular buffering is desired,
disable it prior to issuing this instruction by clearing the Length
Register (
Lreg
) corresponding to the
Ireg
used in this instruction.
Example: If you use
I2
to increment your address pointer, first
clear
L2
to disable circular buffering. Failure to explicitly clear
Lreg
beforehand can result in unexpected
Ireg
values.
The circular address buffer registers (Index, Length, and Base) are
not initialized automatically by Reset. Traditionally, user software
clears all the circular address buffer registers during boot-up to dis-
able circular buffering, then initializes them later, if needed.
Options
(BREV)
–bit reverse carry adder. When specified, the carry bit is propagated
from left to right, as shown in Figure 15-1 , instead of right to left.
When bit reversal is used on the Index Register version of this instruction,
circular buffering is disabled to support operand addressing for FFT,
DCT and DFT algorithms. The Pointer Register version does not support
circular buffering in any case.
Table 15-1. Bit Addition Flow for the Bit Reverse (BREV) Case
an
|
cn
a2
|
c2
a1
|
c1
a0
|
+ + + + c0
|
bn |
b2 |
b1 |
b0