Analog Devices ADSP-BF53x Blackfin, Reference

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Events and Interrupts
4-30 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
An interrupt is an event that changes normal processor instruction flow
and is asynchronous to program flow. In contrast, an exception is a soft-
ware initiated event whose effects are synchronous to program flow.
The event system is nested and prioritized. Consequently, several service
routines may be active at any time, and a low priority event may be
pre-empted by one of higher priority.
The processor employs a two-level event control mechanism. The proces-
sor System Interrupt Controller (SIC) works with the Core Event
Controller (CEC) to prioritize and control all system interrupts. The SIC
provides mapping between the many peripheral interrupt sources and the
prioritized general-purpose interrupt inputs of the core. This mapping is
programmable, and individual interrupt sources can be masked in the
SIC.
The CEC supports nine general-purpose interrupts (
IVG7
–
IVG15
) in
addition to the dedicated interrupt and exception events that are described
in
Table 4-7 . It is recommended that the two lowest priority interrupts
(
IVG14
and
IVG15
) be reserved for software interrupt handlers, leaving
seven prioritized interrupt inputs (
IVG7
–
IVG13
) to support the system.
Refer to the product data sheet for the default system interrupt mapping.
Table 4-7. Core Event Mapping
Event Source Core Event
Name
Core Events Emulation (highest priority) EMU
Reset RST
NMI NMI
Exception EVX
Reserved –
Hardware Error IVHW
Core Timer IVTMR