Analog Devices ADSP-BF53x Blackfin, Reference

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Introduction
4-6 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
In addition to these central sequencer registers, there is a set of mem-
ory-mapped registers that interact closely with the program sequencer. For
information about the interrupt control registers, see
“Events and Inter-
rupts” on page 4-29 . Although the registers of the Core Event Controller
are memory-mapped, they still connect to the same 32-bit Register Access
Bus (RAB) and perform in the same way. Registers of the System Interrupt
Controller connect to the Peripheral Access Bus (PAB) which resides in
the
SCLK
domain. On some derivatives the PAB bus is 16 bits wide; on
others it is 32 bits wide. For debug and test registers see Chapter 21,
“Debug.”
Table 4-1. Non-memory-mapped Sequencer Registers
Register Name Description
SEQSTAT Sequencer Status register: See “Hardware Errors and
Exception Handling” on page 4-58 .
RETX
RETN
RETI
RETE
RETS
Return Address registers: See “Events and Interrupts”
on page 4-29 .
Exception Return
NMI Return
Interrupt Return
Emulation Return
Subroutine Return
LC0, LC1
LT0, LT1
LB0, LB1
Zero-Overhead Loop registers: See “Hardware Loops”
on page 4-21 .:
Loop Counters
Loop Tops
Loop Bottoms
FP, SP Frame Pointer and Stack Pointer: See “Frame and Stack
Pointers” on page 5-6
SYSCFG System Configuration register: See “SYSCFG Register”
on page 21-26
CYCLES, CYCLES2 Cycle Counters: See “CYCLES and CYCLES2 Regis-
ters” on page 21-24
PC Program Counter. The PC is an embedded register. It is
not directly accessible with program instructions.