Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 4-57
Program Sequencer
In order for high priority interrupts to be serviced with the least latency
possible, the processor allows any high latency fill operation to be com-
pleted at the system level, while an interrupt service routine executes from
L1 memory. See
Figure 4-10 .
If an instruction load operation misses the L1 instruction cache and gener-
ates a high latency line fill operation, then when an interrupt occurs, it is
not held off until the fill has completed. Instead, the processor executes
the interrupt service routine in its new context, and the cache fill opera-
tion completes in the background.
Figure 4-10. Minimizing Latency in Servicing an ISR
CLOCK
FETCH
INSTRUCTION
DATA
SERVICED
HERE
FETCH
INSTRUCTION
DATA
INTERRUPT
OCCURRING
HERE SERVICED
HERE
OTHER PROCESSORS
BLACKFIN PROCESSOR
INTERRUPT
OCCURRING
HERE