Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-73
Memory
System MMRs connect to the Peripheral Access Bus (PAB), which is
implemented as either a 16-bit or a 32-bit wide bus on specific derivatives.
The PAB bus operates at
SCLK
rate. Writes to system MMRs do not go
through write buffers nor through store buffers. Rather, there is a simple
bridge between the RAB and the PAB bus that translates between clock
domains (and bus width) only.
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On ADSP-BF535 products only, the system MMRs do reside
behind store and write buffers. There, system MMRs behave like
off-chip I/O devices as described in
“Load/Store Operation” on
page 6-66 . Consequently,
SSYNC
instructions are required after
store instructions to guarantee strong ordering of MMR accesses.
All MMRs are accessible only in Supervisor mode. Access to MMRs in
User mode generates a protection violation exception.
All core MMRs are read and written using 32-bit aligned accesses. How-
ever, some MMRs have fewer than 32 bits defined. In this case, the
unused bits are reserved. System MMRs may be 16 bits.
Accesses to nonexistent MMRs generate an illegal access exception. The
system ignores writes to read-only MMRs.
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Hardware raises an exception when a multi-issue instruction
attempts to simultaneously perform two accesses to MMR space.
Appendix B provides a summary of all Core MMRs.
Core MMR Programming Code Example
Core MMRs may be accessed only as aligned 32-bit words. Nonaligned
access to MMRs generates an exception event.
Listing 6-1 shows the
instructions required to manipulate a generic core MMR.