Analog Devices ADSP-BF53x Blackfin, Reference

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Glossary
1-14 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Functional Units
The architecture includes the three processor sections shown in Table 1-2 .
Loop Count LC0 and LC1; contains 32-bit counter of the zero overhead loop executions.
Loop Bottom LB0 and LB1; contains 32-bit address of the bottom of a zero overhead loop.
Index
Register The set of 32-bit registers I0, I1, I2, I3 that normally contain byte addresses of
data structures. Abbreviated I-register or Ireg.
Modify
Registers The set of 32-bit registers M0, M1, M2, M3 that normally contain offset values
that are added or subtracted to one of the Index Registers. Abbreviated as Mreg.
Length
Registers The set of 32-bit registers L0, L1, L2, L3 that normally contain the length (in
bytes) of the circular buffer. Abbreviated as Lreg. Clear Lreg to disable circular
addressing for the corresponding Ireg. Example: Clear L3 to disable circular
addressing for I3.
Base
Registers The set of 32-bit registers B0, B1, B2, B3 that normally contain the base address
(in bytes) of the circular buffer. Abbreviated as Breg.
Table 1-2. Processor Sections
Processor Description
Data Address
Generator (DAG) Calculates the effective address for indirect and indexed memory
accesses. Consists of two sections–DAG0 and DAG1.
Multiply and
Accumulate Unit
(MAC) Performs the arithmetic functions on data. Consists of two sections
(MAC0 and MAC1)–each associated with an Accumulator (A0 and A1,
respectively).
Arithmetic Logical
Unit (ALU) Performs arithmetic computations and binary shifts on data. Operates
on the Data Registers and Accumulators. Consists of two units (ALU0
and ALU1), each associated with an Accumulator (A0 and A1, respec-
tively). Each ALU operates in conjunction with a Multiply and Accu-
mulate Unit.
Table 1-1. Registers (Cont’d)
Register Description