Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-23
Memory
ITEST_DATA0 Register
The Instruction Test Data 0 register (
ITEST_DATA0
) stores the lower 32
bits of the 64-bit data to be written to or read from by the access. The
ITEST_DATA0
register is also used to access tag arrays. This register also
contains the Valid and Dirty bits, which indicate the state of the cache
line.
Figure 6-8. Instruction Test Data 0 Register
X
X
X X X X X X
X X X X X X X
X X
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X
X
Instruction Test Data 0 Register (ITEST_DATA0)
Reset = Undefined
X
Tag[19:4]
Tag[3:2]
Tag[1:0]
X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X X X X X X X X X X X X X
X X X X X X X X X X X X X X X
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Data[31:16]
Data[15:0]
Used to access L1 cache data arrays and tag arrays. When accessing a data array, stores the lower 32 bits of
64-bit words of instruction data to be written to or read from by the access. See
“Cache Lines” on page 6-10 .
Used to access the L1 cache tag arrays. The address tag consists of the upper 18 bits and bits 11 and 10 of the
physical address. See
“Cache Lines” on page 6-10 .
Physical address
Physical address
Physical address
Reset = Undefined
Valid
0 - Cache line is not valid
1 - Cache line contains valid
data
LRUPRIO
0 - LRUPRIO is cleared for
this entry
1 - LRUPRIO is set for this
entry. See
“ICPLB_DATAx
Registers” on page 6-55 and
“IMEM_CONTROL Register”
on page 6-5
.
0xFFE0 1400