Analog Devices ADSP-BF53x Blackfin, Reference

Page: 712 / 1042

Instruction Overview
19-24 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
Functional Description
The Vector Arithmetic Shift instruction arithmetically shifts a pair of
half-word registered numbers a specified distance and direction. Though
the two half-word registers are shifted at the same time, the two numbers
are kept separate.
Arithmetic right shifts preserve the sign of the preshifted value. The sign
bit value backfills the left-most bit position vacated by the arithmetic right
shift. For positive numbers, this behavior is equivalent to the logical right
shift for unsigned numbers.
Only arithmetic right shifts are supported. Left shifts are performed as
logical left shifts that may not preserve the sign of the original number. In
the default case—without the optional saturation option—numbers can
be left shifted so far that all the sign bits overflow and are lost. However,
when the saturation option is enabled, a left shift that would otherwise
shift nonsign bits off the left side saturates to the maximum positive or
negative value instead. So, with saturation enabled, the result always keeps
the same sign as the original number.
See “Saturation” on page 1-17 for a description of saturation behavior.
“>>>” and “<<” Syntax
The two half-word registers in
dest_reg
are right shifted by the number of
places specified by
shift_magnitude
, and the result stored into
dest_reg
.
The data is always a pair of 16-bit half-registers. Valid
shift_magnitude
values are 0 through 15.