Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
15-64 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
To truncate the result, the operation eliminates the least significant bits
that do not fit into the destination register.
When necessary, saturation is performed after the rounding.
The accumulator is unaffected by extraction.
If you want to keep the unaltered contents of the Accumulator, use a sim-
ple Move instruction to copy
An.X
or
An.W
to or from a register.
See “Saturation” on page 1-17 for a description of saturation behavior.
(IH) Signed integer, high word extract. Multiply 16.0 * 16.0 formats to produce 32.0
results. No shift correction. (Same as the IS mode.)
Sign extend 32.0 result to 40.0 format before copying or accumulating to Accumu-
lator. Then, saturate Accumulator to maintain 32.0 precision; Accumulator result
is between minimum 0x00 8000 0000 and maximum 0x00 7FFF FFFF.
To extract to half-register, round Accumulator 40.0 format value at bit 16.
(RND_MOD bit in the ASTAT register controls the rounding.) Saturate to 32.0
result. Copy the upper 16 bits of that value to the destination register half. Result
is between minimum -2
15
and maximum 2
15
-1 (or, expressed in hex, between min-
imum 0x8000 and maximum 0x7FFF).
(M) Mixed mode multiply (valid only for MAC1). When issued in a fraction mode
instruction (with Default, FU, T, TFU, or S2RND mode), multiply 1.15 * 0.16 to
produce 1.31 results.
When issued in an integer mode instruction (with IS, ISS2, or IH mode), multiply
16.0 * 16.0 (signed * unsigned) to produce 32.0 results.
No shift correction in either case. Src_reg_0 is the signed operand and Src_reg_1
is the unsigned operand.
Accumulation and extraction proceed according to the other mode flag or Default.
Table 15-4. Multiply and Multiply-Accumulate to Half-Register
Options (Cont’d)
Option Description