Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 14-17
Shift/Rotate Operations
The
dest_reg
and
src_reg
can be a 16-, 32-, or 40-bit register.
For the
LSHIFT
instruction, the shift magnitude is the lower 6 bits of the
Dreg_lo
, sign extended. The
Dreg >>= Dreg
and
Dreg <<= Dreg
instruc-
tions use the entire 32 bits of magnitude.
The D-register versions of this instruction shift 16 or 32 bits for half-word
and word registers, respectively. The Accumulator versions shift all 40 bits
of those registers.
Forty-bit Accumulator values can be shifted by up to –32 to +31 bit
places.
Shift magnitudes that exceed the size of the destination register produce
all zeros in the result. For example, shifting a 16-bit register value by 20
bit places (a valid operation) produces 0x0000.
A shift magnitude of zero performs no shift operation at all.
The D-register versions of this instruction do not implicitly modify the
src_reg
values. Optionally,
dest_reg
can be the same D-register as
src_reg
. Doing this explicitly modifies the source register.
Flags Affected
The P-register versions of this instruction do not affect any flags.
The versions of this instruction that send results to a
Dreg
set flags as
follows.
•
AZ
is set if result is zero; cleared if nonzero.
•
AN
is set if result is negative; cleared if non-negative.
•
V
is cleared.
• All other flags are unaffected.