Analog Devices ADSP-BF53x Blackfin, Reference

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Register Files
2-6 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Register Files
The processor’s computational units have three definitive register
groups—a Data Register File, a Pointer Register File, and set of Data
Address Generation (DAG) registers.
• The Data Register File receives operands from the data buses for
the computational units and stores computational results.
• The Pointer Register File has pointers for addressing operations.
• The DAG registers are dedicated registers that manage zero-over-
head circular buffers for DSP operations.
For more information on Pointer and DAG registers, see Chapter 5,
“Address Arithmetic Unit.”
L
In the processor, a word is 32 bits long; H denotes the high order
16 bits of a 32-bit register; L denotes the low order 16 bits of a
32-bit register; W denotes the low order 32 bits of a 40-bit accu-
mulator register; and X denotes the high order 8 bits. For example,
A0.W
contains the lower 32 bits of the 40-bit
A0
register;
A0.L
con-
tains the lower 16 bits of
A0.W
, and
A0.H
contains the upper 16 bits
of
A0.W
.