Analog Devices ADSP-BF53x Blackfin, Reference

Page: 650 / 1042

Instruction Overview
18-10 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
The Dual 16-Bit Add / Clip instruction provides byte alignment directly
in the source register pairs
src_reg_0
and
src_reg_1
based on index regis-
ters
I0
and
I1
.
• The two LSBs of the
I0
register determine the byte alignment for
source register pair
src_reg_0
(typically
R1:0
).
• The two LSBs of the
I1
register determine the byte alignment for
source register pair
src_reg_1
(typically
R3:2
).
The relationship between the I-register bits and the byte alignment is
illustrated in
Table 18-5 .
In the default source order case (for example, not the ( – , R) syntax),
assuming a source register pair contains the following.
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
Options
The ( – , R) syntax reverses the order of the source registers within each
register pair. Typical high performance applications cannot afford the
overhead of reloading both register pair operands to maintain byte order
for every calculation. Instead, they alternate and load only one register
pair operand each time and alternate between the forward and reverse byte
Table 18-5. I-register Bits and the Byte Alignment
The bytes selected are src_reg_pair_HI src_reg_pair_LO
Two LSB’s of I0 or I1 byte7 byte6 byte5 byte4 byte3 byte2 byte1 byte0
00b: byte3 byte2 byte1 byte0
01b: byte4 byte3 byte2 byte1
10b: byte5 byte4 byte3 byte2
11b: byte6 byte5 byte4 byte3