Analog Devices ADSP-BF53x Blackfin, Reference

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L1 Data Memory
6-30 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
If cache is enabled (controlled by bits
DMC[1:0]
in the
DMEM_CONTROL
regis-
ter), data CPLBs should also be enabled (controlled by
ENDCPLB
bit in the
DMEM_CONTROL
register). Only memory pages specified as cacheable by data
CPLBs will be cached. The default behavior when data CPLBs are dis-
abled is for nothing to be cached.
[
Erroneous behavior can result when MMR space is configured as
cacheable by data CPLBs, or when data banks serving as L1 SRAM
are configured as cacheable by data CPLBs.
Example of Mapping Cacheable Address Space
An example of how the cacheable address space maps into two data banks
follows.
When both banks are configured as cache they operate as two indepen-
dent, 16K byte, 2-Way set associative caches that can be independently
mapped into the Blackfin processor address space.
If both data banks are configured as cache, the
DCBS
bit in the
DMEM_CONTROL
register designates Address bit
A[14]
or
A[23]
as the cache
selector. Address bit
A[14]
or
A[23]
selects the cache implemented by
Data Bank A or the cache implemented by Data Bank B.
• If
DCBS = 0
, then
A[14]
is part of the address index, and all
addresses in which
A[14] = 0
use Data Bank B. All addresses in
which
A[14] = 1
use Data Bank A.
In this case,
A[23]
is treated as merely another bit in the address
that is stored with the tag in the cache and compared for hit/miss
processing by the cache.