Analog Devices ADSP-BF53x Blackfin, Reference

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Instruction Overview
15-70 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
The accumulator is unaffected by extraction.
In fractional mode, the product of the most negative representable frac-
tion times itself (for example, 0x8000 times 0x8000) is saturated to the
maximum representable positive fraction (0x7FFF) before accumulation.
If you want to keep the unaltered contents of the Accumulator, use a sim-
ple Move instruction to copy An.X or An.W to or from a register.
See “Saturation” on page 1-17 for a description of saturation behavior.
(ISS2) Signed integer with scaling. Multiply 16.0 * 16.0 formats to produce 32.0 results.
No shift correction. (Same as the IS mode.)
Sign extend 32.0 result to 40.0 format before copying or accumulating to Accumu-
lator. Then, saturate Accumulator to maintain 40.0 precision; Accumulator result
is between minimum 0x80 0000 0000 and maximum 0x7F FFFF FFFF.
To extract, shift the Accumulator contents one place to the left (multiply x 2), sat-
urate the result for 32.0 format, and copy to the destination register. Result is
between minimum -231 and maximum 231-1 (or, expressed in hex, between mini-
mum 0x8000 0000 and maximum 0x7FFF FFFF).
(M) Mixed mode multiply (valid only for MAC1). When issued in a fraction mode
instruction (with Default, FU, T, TFU, or S2RND mode), multiply 1.15 * 0.16 to
produce 1.31 results.
When issued in an integer mode instruction (with IS, ISS2, or IH mode), multiply
16.0 * 16.0 (signed * unsigned) to produce 32.0 results.
No shift correction in either case. Src_reg_0 is the signed operand and Src_reg_1
is the unsigned operand.
Accumulation and extraction proceed according to the other mode flag or Default.
Table 15-5. Multiply and Multiply-Accumulate to Data Register
Options (Cont’d)
Option Description